return ERR_PTR(-ENOMEM);
/* find reset controller when exist */
- pdata->rstc = devm_reset_control_get_optional_exclusive(dev, "reset");
- if (IS_ERR(pdata->rstc))
- return ERR_CAST(pdata->rstc);
+ host->rstc = devm_reset_control_get_optional_exclusive(dev, "reset");
+ if (IS_ERR(host->rstc))
+ return ERR_CAST(host->rstc);
if (device_property_read_u32(dev, "fifo-depth", &pdata->fifo_depth))
dev_info(dev,
goto err_clk_ciu;
}
- if (host->pdata->rstc) {
- reset_control_assert(host->pdata->rstc);
+ if (host->rstc) {
+ reset_control_assert(host->rstc);
usleep_range(10, 50);
- reset_control_deassert(host->pdata->rstc);
+ reset_control_deassert(host->rstc);
}
if (drv_data && drv_data->init) {
if (host->use_dma && host->dma_ops->exit)
host->dma_ops->exit(host);
- reset_control_assert(host->pdata->rstc);
+ reset_control_assert(host->rstc);
err_clk_ciu:
clk_disable_unprepare(host->ciu_clk);
if (host->use_dma && host->dma_ops->exit)
host->dma_ops->exit(host);
- reset_control_assert(host->pdata->rstc);
+ reset_control_assert(host->rstc);
clk_disable_unprepare(host->ciu_clk);
clk_disable_unprepare(host->biu_clk);
* @ctype: Card type for this host.
* @clock: Clock rate configured by set_ios(). Protected by host->lock.
* @clk_old: The last clock value that was requested from core.
+ * @pdev: platform_device registered
+ * @rstc: Reset controller for this host.
*
* Locking
* =======
u32 ctype;
unsigned int clock;
unsigned int clk_old;
+ struct platform_device *pdev;
+ struct reset_control *rstc;
};
/* DMA ops for Internal/External DMAC interface */
/* delay in mS before detecting cards after interrupt */
u32 detect_delay_ms;
-
- struct reset_control *rstc;
};
/* Support for longer data read timeout */