Merge tag 'riscv-for-linus-6.19-rc7' of git://git.kernel.org/pub/scm/linux/kernel...

Pull RISC-V fixes from Paul Walmsley:
 "The notable changes here are the three RISC-V timer compare register
  update sequence patches. These only apply to RV32 systems and are
  related to the 64-bit timer compare value being split across two
  separate 32-bit registers.

  We weren't using the appropriate three-write sequence, documented in
  the RISC-V ISA specifications, to avoid spurious timer interrupts
  during the update sequence; so, these patches now use the recommended
  sequence.

  This doesn't affect 64-bit RISC-V systems, since the timer compare
  value fits inside a single register and can be updated with a single
  write.

   - Fix the RISC-V timer compare register update sequence on RV32
     systems to use the recommended sequence in the RISC-V ISA manual

     This avoids spurious interrupts during updates

   - Add a dependence on the new CONFIG_CACHEMAINT_FOR_DMA Kconfig
     symbol for Renesas and StarFive RISC-V SoCs

   - Add a temporary workaround for a Clang compiler bug caused by using
     asm_goto_output for get_user()

   - Clarify our documentation to specifically state a particular ISA
     specification version for a chapter number reference"

* tag 'riscv-for-linus-6.19-rc7' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux:
  riscv: Add intermediate cast to 'unsigned long' in __get_user_asm
  riscv: Use 64-bit variable for output in __get_user_asm
  soc: renesas: Fix missing dependency on new CONFIG_CACHEMAINT_FOR_DMA
  riscv: ERRATA_STARFIVE_JH7100: Fix missing dependency on new CONFIG_CACHEMAINT_FOR_DMA
  riscv: suspend: Fix stimecmp update hazard on RV32
  riscv: kvm: Fix vstimecmp update hazard on RV32
  riscv: clocksource: Fix stimecmp update hazard on RV32
  Documentation: riscv: uabi: Clarify ISA spec version for canonical order