RISC-V: Adjust testcase asm check for vx-[56]-i[16|8].c

Due to middle-end and new param change, adjust the test cases asm check
as it cannot be vectorized.

	PR/target 123916

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/rvv/autovec/vx_vf/vx-5-i16.c: Adjust the
	asm check to not.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx-5-i8.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i16.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i8.c: Ditto.

Signed-off-by: Pan Li <pan2.li@intel.com>

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-5-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-5-i16.c
index 2209d565d4171df1798b690ab9f8b1015f4d7c8f..a1de51ba1720d5b8b8adf9b5edf59a4f5fbbc6aa 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-5-i16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-5-i16.c
@@ -34,8 +34,8 @@ DEF_VX_BINARY_CASE_3_WRAP(T, AVG_CEIL_FUNC_WRAP(T), avg_ceil, VX_BINARY_FUNC_BOD
 /* { dg-final { scan-assembler {vrem.vx} } } */
 /* { dg-final { scan-assembler {vmax.vx} } } */
 /* { dg-final { scan-assembler {vmin.vx} } } */
-/* { dg-final { scan-assembler {vsadd.vx} } } */
-/* { dg-final { scan-assembler {vssub.vx} } } */
+/* { dg-final { scan-assembler-not {vsadd.vx} } } */
+/* { dg-final { scan-assembler-not {vssub.vx} } } */
 /* { dg-final { scan-assembler {vaadd.vx} { target { any-opts {
      "-mrvv-vector-bits=zvl -mrvv-max-lmul=m1"
      "-mrvv-vector-bits=zvl -mrvv-max-lmul=m2"

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-5-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-5-i8.c
index 26610a6f8397846b8fb10e09319398a60388ab86..86f9a29b5f9fc6d5ec89c6802cd76b07902a8a2d 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-5-i8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-5-i8.c
@@ -34,8 +34,8 @@ DEF_VX_BINARY_CASE_3_WRAP(T, AVG_CEIL_FUNC_WRAP(T), avg_ceil, VX_BINARY_FUNC_BOD
 /* { dg-final { scan-assembler {vrem.vx} } } */
 /* { dg-final { scan-assembler {vmax.vx} } } */
 /* { dg-final { scan-assembler {vmin.vx} } } */
-/* { dg-final { scan-assembler {vsadd.vx} } } */
-/* { dg-final { scan-assembler {vssub.vx} } } */
+/* { dg-final { scan-assembler-not {vsadd.vx} } } */
+/* { dg-final { scan-assembler-not {vssub.vx} } } */
 /* { dg-final { scan-assembler {vaadd.vx} { target { no-opts {
      "-mrvv-vector-bits=zvl -mrvv-max-lmul=m1"
      "-mrvv-vector-bits=zvl -mrvv-max-lmul=m2"

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i16.c
index 326971b4bd0a7789e3f1e2214b57c5cbe652bdbf..58730d0a0d4b35680b9c09fdfac5e6e9330a89ea 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i16.c
@@ -34,8 +34,8 @@ DEF_VX_BINARY_CASE_3_WRAP(T, AVG_CEIL_FUNC_WRAP(T), avg_ceil, VX_BINARY_FUNC_BOD
 /* { dg-final { scan-assembler {vrem.vx} } } */
 /* { dg-final { scan-assembler {vmax.vx} } } */
 /* { dg-final { scan-assembler {vmin.vx} } } */
-/* { dg-final { scan-assembler {vsadd.vx} } } */
-/* { dg-final { scan-assembler {vssub.vx} } } */
+/* { dg-final { scan-assembler-not {vsadd.vx} } } */
+/* { dg-final { scan-assembler-not {vssub.vx} } } */
 /* { dg-final { scan-assembler {vaadd.vx} { target { any-opts {
      "-mrvv-vector-bits=zvl -mrvv-max-lmul=m1"
      "-mrvv-vector-bits=zvl -mrvv-max-lmul=m2"

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i8.c
index c03f23346c0d069a24f34d7316ad565279a20c7c..f1eece7266fdd2a0adaad3889bfc3c5906815dec 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i8.c
@@ -34,8 +34,8 @@ DEF_VX_BINARY_CASE_3_WRAP(T, AVG_CEIL_FUNC_WRAP(T), avg_ceil, VX_BINARY_FUNC_BOD
 /* { dg-final { scan-assembler {vrem.vx} } } */
 /* { dg-final { scan-assembler {vmax.vx} } } */
 /* { dg-final { scan-assembler {vmin.vx} } } */
-/* { dg-final { scan-assembler {vsadd.vx} } } */
-/* { dg-final { scan-assembler {vssub.vx} } } */
+/* { dg-final { scan-assembler-not {vsadd.vx} } } */
+/* { dg-final { scan-assembler-not {vssub.vx} } } */
 /* { dg-final { scan-assembler {vaadd.vx} { target { any-opts {
      "-mrvv-vector-bits=zvl -mrvv-max-lmul=m1"
      "-mrvv-vector-bits=zvl -mrvv-max-lmul=m2"