ASoC: rockchip: spdif: Convert to FIELD_PREP

Convert the driver to use FIELD_PREP to increase readability.
This also fixes an issue that the SDPIF_CFGR_VDW_MASK was wrong,
which didn't have any effects as the only user in the driver
updates the other bits at the same time.

Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
Link: https://patch.msgid.link/20260203-rockchip-spdif-cleanup-and-bsp-sync-v2-10-4412016cf577@collabora.com
Signed-off-by: Mark Brown <broonie@kernel.org>

diff --git a/sound/soc/rockchip/rockchip_spdif.c b/sound/soc/rockchip/rockchip_spdif.c
index e64c24897f29a6e6f5a78049302c570707eb28b7..581624f2682ef3ca397fd7234a96dead7223e171 100644 (file)
--- a/sound/soc/rockchip/rockchip_spdif.c
+++ b/sound/soc/rockchip/rockchip_spdif.c
@@ -5,10 +5,11 @@
  *
  * Copyright (c) 2014 Rockchip Electronics Co. Ltd.
  * Author: Jianqun <jay.xu@rock-chips.com>
- * Copyright (c) 2015 Collabora Ltd.
+ * Copyright (c) 2015-2026 Collabora Ltd.
  * Author: Sjoerd Simons <sjoerd.simons@collabora.co.uk>
  */
 
+#include <linux/bitfield.h>
 #include <linux/module.h>
 #include <linux/delay.h>
 #include <linux/clk.h>
@@ -159,7 +160,7 @@ static int rk_spdif_hw_params(struct snd_pcm_substream *substream,
 
        ret = regmap_update_bits(spdif->regmap, SPDIF_CFGR,
                                 SPDIF_CFGR_CLK_DIV_MASK |
-                                SPDIF_CFGR_HALFWORD_ENABLE |
+                                SPDIF_CFGR_HALFWORD_MASK |
                                 SDPIF_CFGR_VDW_MASK |
                                 SPDIF_CFGR_ADJ_MASK, val);
 
@@ -177,7 +178,7 @@ static int rk_spdif_trigger(struct snd_pcm_substream *substream,
        case SNDRV_PCM_TRIGGER_RESUME:
        case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
                ret = regmap_update_bits(spdif->regmap, SPDIF_DMACR,
-                                        SPDIF_DMACR_TDE_ENABLE |
+                                        SPDIF_DMACR_TDE_MASK |
                                         SPDIF_DMACR_TDL_MASK,
                                         SPDIF_DMACR_TDE_ENABLE |
                                         SPDIF_DMACR_TDL(16));
@@ -186,21 +187,21 @@ static int rk_spdif_trigger(struct snd_pcm_substream *substream,
                        return ret;
 
                ret = regmap_update_bits(spdif->regmap, SPDIF_XFER,
-                                        SPDIF_XFER_TXS_START,
+                                        SPDIF_XFER_TXS_MASK,
                                         SPDIF_XFER_TXS_START);
                break;
        case SNDRV_PCM_TRIGGER_SUSPEND:
        case SNDRV_PCM_TRIGGER_STOP:
        case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
                ret = regmap_update_bits(spdif->regmap, SPDIF_DMACR,
-                                        SPDIF_DMACR_TDE_ENABLE,
+                                        SPDIF_DMACR_TDE_MASK,
                                         SPDIF_DMACR_TDE_DISABLE);
 
                if (ret != 0)
                        return ret;
 
                ret = regmap_update_bits(spdif->regmap, SPDIF_XFER,
-                                        SPDIF_XFER_TXS_START,
+                                        SPDIF_XFER_TXS_MASK,
                                         SPDIF_XFER_TXS_STOP);
                break;
        default:

diff --git a/sound/soc/rockchip/rockchip_spdif.h b/sound/soc/rockchip/rockchip_spdif.h
index b837b1f8d57f3538d023a0ab747bcfcd8cb83f62..ec33295e2512807d8476d4cf1bec6eec554841a7 100644 (file)
--- a/sound/soc/rockchip/rockchip_spdif.h
+++ b/sound/soc/rockchip/rockchip_spdif.h
@@ -2,7 +2,7 @@
 /*
  * ALSA SoC Audio Layer - Rockchip SPDIF transceiver driver
  *
- * Copyright (c) 2015 Collabora Ltd.
+ * Copyright (c) 2015-2026 Collabora Ltd.
  * Author: Sjoerd Simons <sjoerd.simons@collabora.co.uk>
  */
 
@@ -13,53 +13,50 @@
  * CFGR
  * transfer configuration register
 */
-#define SPDIF_CFGR_CLK_DIV_SHIFT       (16)
-#define SPDIF_CFGR_CLK_DIV_MASK                (0xff << SPDIF_CFGR_CLK_DIV_SHIFT)
-#define SPDIF_CFGR_CLK_DIV(x)          ((x-1) << SPDIF_CFGR_CLK_DIV_SHIFT)
+#define SPDIF_CFGR_CLK_DIV_MASK                GENMASK(23, 16)
+#define SPDIF_CFGR_CLK_DIV(x)          FIELD_PREP(SPDIF_CFGR_CLK_DIV_MASK, x-1)
 
 #define SPDIF_CFGR_CLR_MASK            BIT(7)
-#define SPDIF_CFGR_CLR_EN              BIT(7)
-#define SPDIF_CFGR_CLR_DIS             0
+#define SPDIF_CFGR_CLR_EN              FIELD_PREP(SPDIF_CFGR_CLR_MASK, 1)
+#define SPDIF_CFGR_CLR_DIS             FIELD_PREP(SPDIF_CFGR_CLR_MASK, 0)
 
 #define SPDIF_CFGR_CSE_MASK            BIT(6)
-#define SPDIF_CFGR_CSE_EN              BIT(6)
-#define SPDIF_CFGR_CSE_DIS             0
+#define SPDIF_CFGR_CSE_EN              FIELD_PREP(SPDIF_CFGR_CSE_MASK, 1)
+#define SPDIF_CFGR_CSE_DIS             FIELD_PREP(SPDIF_CFGR_CSE_MASK, 0)
 
 #define SPDIF_CFGR_ADJ_MASK            BIT(3)
-#define SPDIF_CFGR_ADJ_LEFT_J          BIT(3)
-#define SPDIF_CFGR_ADJ_RIGHT_J         0
+#define SPDIF_CFGR_ADJ_LEFT_J          FIELD_PREP(SPDIF_CFGR_ADJ_MASK, 1)
+#define SPDIF_CFGR_ADJ_RIGHT_J         FIELD_PREP(SPDIF_CFGR_ADJ_MASK, 0)
 
-#define SPDIF_CFGR_HALFWORD_SHIFT      2
-#define SPDIF_CFGR_HALFWORD_DISABLE    (0 << SPDIF_CFGR_HALFWORD_SHIFT)
-#define SPDIF_CFGR_HALFWORD_ENABLE     (1 << SPDIF_CFGR_HALFWORD_SHIFT)
+#define SPDIF_CFGR_HALFWORD_MASK       BIT(2)
+#define SPDIF_CFGR_HALFWORD_DISABLE    FIELD_PREP(SPDIF_CFGR_HALFWORD_MASK, 0)
+#define SPDIF_CFGR_HALFWORD_ENABLE     FIELD_PREP(SPDIF_CFGR_HALFWORD_MASK, 1)
 
-#define SPDIF_CFGR_VDW_SHIFT   0
-#define SPDIF_CFGR_VDW(x)      (x << SPDIF_CFGR_VDW_SHIFT)
-#define SDPIF_CFGR_VDW_MASK    (0xf << SPDIF_CFGR_VDW_SHIFT)
+#define SDPIF_CFGR_VDW_MASK            GENMASK(1, 0)
+#define SPDIF_CFGR_VDW(x)              FIELD_PREP(SDPIF_CFGR_VDW_MASK, x)
 
-#define SPDIF_CFGR_VDW_16      SPDIF_CFGR_VDW(0x0)
-#define SPDIF_CFGR_VDW_20      SPDIF_CFGR_VDW(0x1)
-#define SPDIF_CFGR_VDW_24      SPDIF_CFGR_VDW(0x2)
+#define SPDIF_CFGR_VDW_16              SPDIF_CFGR_VDW(0x0)
+#define SPDIF_CFGR_VDW_20              SPDIF_CFGR_VDW(0x1)
+#define SPDIF_CFGR_VDW_24              SPDIF_CFGR_VDW(0x2)
 
 /*
  * DMACR
  * DMA control register
 */
-#define SPDIF_DMACR_TDE_SHIFT  5
-#define SPDIF_DMACR_TDE_DISABLE        (0 << SPDIF_DMACR_TDE_SHIFT)
-#define SPDIF_DMACR_TDE_ENABLE (1 << SPDIF_DMACR_TDE_SHIFT)
+#define SPDIF_DMACR_TDE_MASK           BIT(5)
+#define SPDIF_DMACR_TDE_DISABLE                FIELD_PREP(SPDIF_DMACR_TDE_MASK, 0)
+#define SPDIF_DMACR_TDE_ENABLE         FIELD_PREP(SPDIF_DMACR_TDE_MASK, 1)
 
-#define SPDIF_DMACR_TDL_SHIFT  0
-#define SPDIF_DMACR_TDL(x)     ((x) << SPDIF_DMACR_TDL_SHIFT)
-#define SPDIF_DMACR_TDL_MASK   (0x1f << SPDIF_DMACR_TDL_SHIFT)
+#define SPDIF_DMACR_TDL_MASK           GENMASK(4, 0)
+#define SPDIF_DMACR_TDL(x)             FIELD_PREP(SPDIF_DMACR_TDL_MASK, x)
 
 /*
  * XFER
  * Transfer control register
 */
-#define SPDIF_XFER_TXS_SHIFT   0
-#define SPDIF_XFER_TXS_STOP    (0 << SPDIF_XFER_TXS_SHIFT)
-#define SPDIF_XFER_TXS_START   (1 << SPDIF_XFER_TXS_SHIFT)
+#define SPDIF_XFER_TXS_MASK            BIT(0)
+#define SPDIF_XFER_TXS_STOP            FIELD_PREP(SPDIF_XFER_TXS_MASK, 0)
+#define SPDIF_XFER_TXS_START           FIELD_PREP(SPDIF_XFER_TXS_MASK, 1)
 
 #define SPDIF_CFGR     (0x0000)
 #define SPDIF_SDBLR    (0x0004)