crypto: qat - disable ZUC-256 capability for QAT GEN5

The ZUC-256 EEA (encryption) and EIA (integrity) algorithms are not
supported on QAT GEN5 devices, as their current implementation does not
align with the NIST specification. Earlier versions of the ZUC-256
specification used a different initialization scheme, which has since
been revised to comply with the 5G specification.

Due to this misalignment with the updated specification, remove support
for ZUC-256 EEA and EIA for QAT GEN5 by masking out the ZUC-256
capability.

Fixes: fcf60f4bcf549 ("crypto: qat - add support for 420xx devices")
Signed-off-by: Bairavi Alagappan <bairavix.alagappan@intel.com>
Signed-off-by: Giovanni Cabiddu <giovanni.cabiddu@intel.com>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>

diff --git a/drivers/crypto/intel/qat/qat_420xx/adf_420xx_hw_data.c b/drivers/crypto/intel/qat/qat_420xx/adf_420xx_hw_data.c
index 7c3c0f561c956203c03f599bc3829a5555b05ddc..8340b5e8a94714f5850d8d3cacf90a2c5268845e 100644 (file)
--- a/drivers/crypto/intel/qat/qat_420xx/adf_420xx_hw_data.c
+++ b/drivers/crypto/intel/qat/qat_420xx/adf_420xx_hw_data.c
@@ -191,7 +191,6 @@ static u32 get_accel_cap(struct adf_accel_dev *accel_dev)
                          ICP_ACCEL_CAPABILITIES_SM4 |
                          ICP_ACCEL_CAPABILITIES_AES_V2 |
                          ICP_ACCEL_CAPABILITIES_ZUC |
-                         ICP_ACCEL_CAPABILITIES_ZUC_256 |
                          ICP_ACCEL_CAPABILITIES_WIRELESS_CRYPTO_EXT |
                          ICP_ACCEL_CAPABILITIES_EXT_ALGCHAIN;
 
@@ -223,17 +222,11 @@ static u32 get_accel_cap(struct adf_accel_dev *accel_dev)
 
        if (fusectl1 & ICP_ACCEL_GEN4_MASK_WCP_WAT_SLICE) {
                capabilities_sym &= ~ICP_ACCEL_CAPABILITIES_ZUC;
-               capabilities_sym &= ~ICP_ACCEL_CAPABILITIES_ZUC_256;
                capabilities_sym &= ~ICP_ACCEL_CAPABILITIES_WIRELESS_CRYPTO_EXT;
        }
 
-       if (fusectl1 & ICP_ACCEL_GEN4_MASK_EIA3_SLICE) {
+       if (fusectl1 & ICP_ACCEL_GEN4_MASK_EIA3_SLICE)
                capabilities_sym &= ~ICP_ACCEL_CAPABILITIES_ZUC;
-               capabilities_sym &= ~ICP_ACCEL_CAPABILITIES_ZUC_256;
-       }
-
-       if (fusectl1 & ICP_ACCEL_GEN4_MASK_ZUC_256_SLICE)
-               capabilities_sym &= ~ICP_ACCEL_CAPABILITIES_ZUC_256;
 
        capabilities_asym = ICP_ACCEL_CAPABILITIES_CRYPTO_ASYMMETRIC |
                          ICP_ACCEL_CAPABILITIES_SM2 |