#define MI_FORCE_WAKEUP __MI_INSTR(0x1D)
#define MI_MATH(n) (__MI_INSTR(0x1A) | XE_INSTR_NUM_DW((n) + 1))
+#define MI_SEMAPHORE_WAIT (__MI_INSTR(0x1c) | XE_INSTR_NUM_DW(5))
+#define MI_SEMW_GGTT REG_BIT(22)
+#define MI_SEMW_POLL REG_BIT(15)
+#define MI_SEMW_COMPARE_OP_MASK REG_GENMASK(14, 12)
+#define COMPARE_OP_SAD_GT_SDD 0
+#define COMPARE_OP_SAD_GTE_SDD 1
+#define COMPARE_OP_SAD_LT_SDD 2
+#define COMPARE_OP_SAD_LTE_SDD 3
+#define COMPARE_OP_SAD_EQ_SDD 4
+#define COMPARE_OP_SAD_NEQ_SDD 5
+#define MI_SEMW_COMPARE(OP) REG_FIELD_PREP(MI_SEMW_COMPARE_OP_MASK, COMPARE_OP_##OP)
+#define MI_SEMW_TOKEN(token) REG_FIELD_PREP(REG_GENMASK(9, 2), (token))
+
#define MI_STORE_DATA_IMM __MI_INSTR(0x20)
#define MI_SDI_GGTT REG_BIT(22)
#define MI_SDI_LEN_DW GENMASK(9, 0)