MIPS: Don't clobber CP0_STATUS value for CONFIG_MIPS_MT_SMTC

Reported-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
Signed-off-by: David Daney <david.daney@cavium.com>
Patchwork: https://patchwork.linux-mips.org/patch/2753/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

diff --git a/arch/mips/include/asm/stackframe.h b/arch/mips/include/asm/stackframe.h
index b4ba2449444b33101c33d4e9d7fd17b968db8466..cb41af5f3406cbddc91e23633463fe6a3b65e769 100644 (file)
--- a/arch/mips/include/asm/stackframe.h
+++ b/arch/mips/include/asm/stackframe.h
@@ -195,9 +195,9 @@
                 * to cover the pipeline delay.
                 */
                .set    mips32
-               mfc0    v1, CP0_TCSTATUS
+               mfc0    k0, CP0_TCSTATUS
                .set    mips0
-               LONG_S  v1, PT_TCSTATUS(sp)
+               LONG_S  k0, PT_TCSTATUS(sp)
 #endif /* CONFIG_MIPS_MT_SMTC */
                LONG_S  $4, PT_R4(sp)
                LONG_S  $5, PT_R5(sp)