Remove upstreamed patches and refresh remaining ones for 6.12.
Signed-off-by: Zoltan HERPAI <wigyori@uid0.hu>
+++ /dev/null
-From 951992797378a2177946400438f4d23c9fceae5b Mon Sep 17 00:00:00 2001
-From: Martin Botka <martin.botka@somainline.org>
-Date: Tue, 12 Sep 2023 14:25:13 +0200
-Subject: [PATCH] arm64: dts: allwinner: h616: Add SID controller node
-
-Add node for the H616 SID controller
-
-Signed-off-by: Martin Botka <martin.botka@somainline.org>
-Acked-by: Jernej Skrabec <jernej.skrabec@gmail.com>
-Link: https://lore.kernel.org/r/20230912-sid-h616-v3-2-ee18e1c5bbb5@somainline.org
-Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
----
- arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi | 7 +++++++
- 1 file changed, 7 insertions(+)
-
---- a/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi
-+++ b/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi
-@@ -133,6 +133,13 @@
- #reset-cells = <1>;
- };
-
-+ sid: efuse@3006000 {
-+ compatible = "allwinner,sun50i-h616-sid", "allwinner,sun50i-a64-sid";
-+ reg = <0x03006000 0x1000>;
-+ #address-cells = <1>;
-+ #size-cells = <1>;
-+ };
-+
- watchdog: watchdog@30090a0 {
- compatible = "allwinner,sun50i-h616-wdt",
- "allwinner,sun6i-a31-wdt";
+++ /dev/null
-From 898d96c5464b69af44f6407c5de81ebc349d574b Mon Sep 17 00:00:00 2001
-From: Andre Przywara <andre.przywara@arm.com>
-Date: Mon, 19 Feb 2024 15:36:33 +0000
-Subject: [PATCH] soc: sunxi: sram: export register 0 for THS on H616
-
-The Allwinner H616 SoC contains a mysterious bit at register offset 0x0
-in the SRAM control block. If bit 16 is set (the reset value), the
-temperature readings of the THS are way off, leading to reports about
-200C, at normal ambient temperatures. Clearing this bits brings the
-reported values down to the expected values.
-The BSP code clears this bit in firmware (U-Boot), and has an explicit
-comment about this, but offers no real explanation.
-
-Experiments in U-Boot show that register 0x0 has no effect on the SRAM C
-visibility: all tested bit settings still allow full read and write
-access by the CPU to the whole of SRAM C. Only bit 24 of the register at
-offset 0x4 makes all of SRAM C inaccessible by the CPU. So modelling
-the THS switch functionality as an SRAM region would not reflect reality.
-
-Since we should not rely on firmware settings, allow other code (the THS
-driver) to access this register, by exporting it through the already
-existing regmap. This mimics what we already do for the LDO control and
-the EMAC register.
-
-To avoid concurrent accesses to the same register at the same time, by
-the SRAM switch code and the regmap code, use the same lock to protect
-the access. The regmap subsystem allows to use an existing lock, so we
-just need to hook in there.
-
-Signed-off-by: Andre Przywara <andre.przywara@arm.com>
-Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com>
-Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
-Link: https://lore.kernel.org/r/20240219153639.179814-2-andre.przywara@arm.com
----
- drivers/soc/sunxi/sunxi_sram.c | 22 ++++++++++++++++++++++
- 1 file changed, 22 insertions(+)
-
---- a/drivers/soc/sunxi/sunxi_sram.c
-+++ b/drivers/soc/sunxi/sunxi_sram.c
-@@ -287,6 +287,7 @@ EXPORT_SYMBOL(sunxi_sram_release);
- struct sunxi_sramc_variant {
- int num_emac_clocks;
- bool has_ldo_ctrl;
-+ bool has_ths_offset;
- };
-
- static const struct sunxi_sramc_variant sun4i_a10_sramc_variant = {
-@@ -308,8 +309,10 @@ static const struct sunxi_sramc_variant
-
- static const struct sunxi_sramc_variant sun50i_h616_sramc_variant = {
- .num_emac_clocks = 2,
-+ .has_ths_offset = true,
- };
-
-+#define SUNXI_SRAM_THS_OFFSET_REG 0x0
- #define SUNXI_SRAM_EMAC_CLOCK_REG 0x30
- #define SUNXI_SYS_LDO_CTRL_REG 0x150
-
-@@ -318,6 +321,8 @@ static bool sunxi_sram_regmap_accessible
- {
- const struct sunxi_sramc_variant *variant = dev_get_drvdata(dev);
-
-+ if (reg == SUNXI_SRAM_THS_OFFSET_REG && variant->has_ths_offset)
-+ return true;
- if (reg >= SUNXI_SRAM_EMAC_CLOCK_REG &&
- reg < SUNXI_SRAM_EMAC_CLOCK_REG + variant->num_emac_clocks * 4)
- return true;
-@@ -327,6 +332,20 @@ static bool sunxi_sram_regmap_accessible
- return false;
- }
-
-+static void sunxi_sram_lock(void *_lock)
-+{
-+ spinlock_t *lock = _lock;
-+
-+ spin_lock(lock);
-+}
-+
-+static void sunxi_sram_unlock(void *_lock)
-+{
-+ spinlock_t *lock = _lock;
-+
-+ spin_unlock(lock);
-+}
-+
- static struct regmap_config sunxi_sram_regmap_config = {
- .reg_bits = 32,
- .val_bits = 32,
-@@ -336,6 +355,9 @@ static struct regmap_config sunxi_sram_r
- /* other devices have no business accessing other registers */
- .readable_reg = sunxi_sram_regmap_accessible_reg,
- .writeable_reg = sunxi_sram_regmap_accessible_reg,
-+ .lock = sunxi_sram_lock,
-+ .unlock = sunxi_sram_unlock,
-+ .lock_arg = &sram_lock,
- };
-
- static int __init sunxi_sram_probe(struct platform_device *pdev)
+++ /dev/null
-From ebbf19e36d021f253425344b4d4b987f3b7d9be5 Mon Sep 17 00:00:00 2001
-From: Maxim Kiselev <bigunclemax@gmail.com>
-Date: Mon, 18 Dec 2023 00:06:23 +0300
-Subject: [PATCH] thermal/drivers/sun8i: Add D1/T113s THS controller support
-
-This patch adds a thermal sensor controller support for the D1/T113s,
-which is similar to the one on H6, but with only one sensor and
-different scale and offset values.
-
-Signed-off-by: Maxim Kiselev <bigunclemax@gmail.com>
-Acked-by: Jernej Skrabec <jernej.skrabec@gmail.com>
-Reviewed-by: Andre Przywara <andre.przywara@arm.com>
-Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
-Link: https://lore.kernel.org/r/20231217210629.131486-3-bigunclemax@gmail.com
----
- drivers/thermal/sun8i_thermal.c | 13 +++++++++++++
- 1 file changed, 13 insertions(+)
-
---- a/drivers/thermal/sun8i_thermal.c
-+++ b/drivers/thermal/sun8i_thermal.c
-@@ -606,6 +606,18 @@ static const struct ths_thermal_chip sun
- .calc_temp = sun8i_ths_calc_temp,
- };
-
-+static const struct ths_thermal_chip sun20i_d1_ths = {
-+ .sensor_num = 1,
-+ .has_bus_clk_reset = true,
-+ .offset = 188552,
-+ .scale = 673,
-+ .temp_data_base = SUN50I_H6_THS_TEMP_DATA,
-+ .calibrate = sun50i_h6_ths_calibrate,
-+ .init = sun50i_h6_thermal_init,
-+ .irq_ack = sun50i_h6_irq_ack,
-+ .calc_temp = sun8i_ths_calc_temp,
-+};
-+
- static const struct of_device_id of_ths_match[] = {
- { .compatible = "allwinner,sun8i-a83t-ths", .data = &sun8i_a83t_ths },
- { .compatible = "allwinner,sun8i-h3-ths", .data = &sun8i_h3_ths },
-@@ -614,6 +626,7 @@ static const struct of_device_id of_ths_
- { .compatible = "allwinner,sun50i-a100-ths", .data = &sun50i_a100_ths },
- { .compatible = "allwinner,sun50i-h5-ths", .data = &sun50i_h5_ths },
- { .compatible = "allwinner,sun50i-h6-ths", .data = &sun50i_h6_ths },
-+ { .compatible = "allwinner,sun20i-d1-ths", .data = &sun20i_d1_ths },
- { /* sentinel */ },
- };
- MODULE_DEVICE_TABLE(of, of_ths_match);
+++ /dev/null
-From 14f118aa50fe7c7c7330f56d007ecacca487cea8 Mon Sep 17 00:00:00 2001
-From: Andre Przywara <andre.przywara@arm.com>
-Date: Mon, 19 Feb 2024 15:36:35 +0000
-Subject: [PATCH] thermal/drivers/sun8i: Explain unknown H6 register value
-
-So far we were ORing in some "unknown" value into the THS control
-register on the Allwinner H6. This part of the register is not explained
-in the H6 manual, but the H616 manual details those bits, and on closer
-inspection the THS IP blocks in both SoCs seem very close:
-- The BSP code for both SoCs writes the same values into THS_CTRL.
-- The reset values of at least the first three registers are the same.
-
-Replace the "unknown" value with its proper meaning: "acquire time",
-most probably the sample part of the sample & hold circuit of the ADC,
-according to its explanation in the H616 manual.
-
-No functional change, just a macro rename and adjustment.
-
-Signed-off-by: Andre Przywara <andre.przywara@arm.com>
-Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com>
-Acked-by: Vasily Khoruzhick <anarsoul@gmail.com>
-Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
-Link: https://lore.kernel.org/r/20240219153639.179814-4-andre.przywara@arm.com
----
- drivers/thermal/sun8i_thermal.c | 29 ++++++++++++++++-------------
- 1 file changed, 16 insertions(+), 13 deletions(-)
-
---- a/drivers/thermal/sun8i_thermal.c
-+++ b/drivers/thermal/sun8i_thermal.c
-@@ -50,7 +50,8 @@
- #define SUN8I_THS_CTRL2_T_ACQ1(x) ((GENMASK(15, 0) & (x)) << 16)
- #define SUN8I_THS_DATA_IRQ_STS(x) BIT(x + 8)
-
--#define SUN50I_THS_CTRL0_T_ACQ(x) ((GENMASK(15, 0) & (x)) << 16)
-+#define SUN50I_THS_CTRL0_T_ACQ(x) (GENMASK(15, 0) & ((x) - 1))
-+#define SUN50I_THS_CTRL0_T_SAMPLE_PER(x) ((GENMASK(15, 0) & ((x) - 1)) << 16)
- #define SUN50I_THS_FILTER_EN BIT(2)
- #define SUN50I_THS_FILTER_TYPE(x) (GENMASK(1, 0) & (x))
- #define SUN50I_H6_THS_PC_TEMP_PERIOD(x) ((GENMASK(19, 0) & (x)) << 12)
-@@ -410,25 +411,27 @@ static int sun8i_h3_thermal_init(struct
- return 0;
- }
-
--/*
-- * Without this undocumented value, the returned temperatures would
-- * be higher than real ones by about 20C.
-- */
--#define SUN50I_H6_CTRL0_UNK 0x0000002f
--
- static int sun50i_h6_thermal_init(struct ths_device *tmdev)
- {
- int val;
-
- /*
-- * T_acq = 20us
-- * clkin = 24MHz
-- *
-- * x = T_acq * clkin - 1
-- * = 479
-+ * The manual recommends an overall sample frequency of 50 KHz (20us,
-+ * 480 cycles at 24 MHz), which provides plenty of time for both the
-+ * acquisition time (>24 cycles) and the actual conversion time
-+ * (>14 cycles).
-+ * The lower half of the CTRL register holds the "acquire time", in
-+ * clock cycles, which the manual recommends to be 2us:
-+ * 24MHz * 2us = 48 cycles.
-+ * The high half of THS_CTRL encodes the sample frequency, in clock
-+ * cycles: 24MHz * 20us = 480 cycles.
-+ * This is explained in the H616 manual, but apparently wrongly
-+ * described in the H6 manual, although the BSP code does the same
-+ * for both SoCs.
- */
- regmap_write(tmdev->regmap, SUN50I_THS_CTRL0,
-- SUN50I_H6_CTRL0_UNK | SUN50I_THS_CTRL0_T_ACQ(479));
-+ SUN50I_THS_CTRL0_T_ACQ(48) |
-+ SUN50I_THS_CTRL0_T_SAMPLE_PER(480));
- /* average over 4 samples */
- regmap_write(tmdev->regmap, SUN50I_H6_THS_MFC,
- SUN50I_THS_FILTER_EN |
+++ /dev/null
-From 6c04a419a4c5fb18edefc44dd676fb95c7f6c55d Mon Sep 17 00:00:00 2001
-From: Maksim Kiselev <bigunclemax@gmail.com>
-Date: Mon, 19 Feb 2024 15:36:36 +0000
-Subject: [PATCH] thermal/drivers/sun8i: Extend H6 calibration to support 4
- sensors
-
-The H616 SoC resembles the H6 thermal sensor controller, with a few
-changes like four sensors.
-
-Extend sun50i_h6_ths_calibrate() function to support calibration of
-these sensors.
-
-Co-developed-by: Martin Botka <martin.botka@somainline.org>
-Signed-off-by: Martin Botka <martin.botka@somainline.org>
-Signed-off-by: Maksim Kiselev <bigunclemax@gmail.com>
-Reviewed-by: Andre Przywara <andre.przywara@arm.com>
-Signed-off-by: Andre Przywara <andre.przywara@arm.com>
-Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com>
-Acked-by: Vasily Khoruzhick <anarsoul@gmail.com>
-Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
-Link: https://lore.kernel.org/r/20240219153639.179814-5-andre.przywara@arm.com
----
- drivers/thermal/sun8i_thermal.c | 28 ++++++++++++++++++++--------
- 1 file changed, 20 insertions(+), 8 deletions(-)
-
---- a/drivers/thermal/sun8i_thermal.c
-+++ b/drivers/thermal/sun8i_thermal.c
-@@ -222,16 +222,21 @@ static int sun50i_h6_ths_calibrate(struc
- struct device *dev = tmdev->dev;
- int i, ft_temp;
-
-- if (!caldata[0] || callen < 2 + 2 * tmdev->chip->sensor_num)
-+ if (!caldata[0])
- return -EINVAL;
-
- /*
- * efuse layout:
- *
-- * 0 11 16 32
-- * +-------+-------+-------+
-- * |temp| |sensor0|sensor1|
-- * +-------+-------+-------+
-+ * 0 11 16 27 32 43 48 57
-+ * +----------+-----------+-----------+-----------+
-+ * | temp | |sensor0| |sensor1| |sensor2| |
-+ * +----------+-----------+-----------+-----------+
-+ * ^ ^ ^
-+ * | | |
-+ * | | sensor3[11:8]
-+ * | sensor3[7:4]
-+ * sensor3[3:0]
- *
- * The calibration data on the H6 is the ambient temperature and
- * sensor values that are filled during the factory test stage.
-@@ -244,9 +249,16 @@ static int sun50i_h6_ths_calibrate(struc
- ft_temp = (caldata[0] & FT_TEMP_MASK) * 100;
-
- for (i = 0; i < tmdev->chip->sensor_num; i++) {
-- int sensor_reg = caldata[i + 1] & TEMP_CALIB_MASK;
-- int cdata, offset;
-- int sensor_temp = tmdev->chip->calc_temp(tmdev, i, sensor_reg);
-+ int sensor_reg, sensor_temp, cdata, offset;
-+
-+ if (i == 3)
-+ sensor_reg = (caldata[1] >> 12)
-+ | ((caldata[2] >> 12) << 4)
-+ | ((caldata[3] >> 12) << 8);
-+ else
-+ sensor_reg = caldata[i + 1] & TEMP_CALIB_MASK;
-+
-+ sensor_temp = tmdev->chip->calc_temp(tmdev, i, sensor_reg);
-
- /*
- * Calibration data is CALIBRATE_DEFAULT - (calculated
+++ /dev/null
-From f8b54d1120b81ed57bed96cc8e814ba08886d1e5 Mon Sep 17 00:00:00 2001
-From: Andre Przywara <andre.przywara@arm.com>
-Date: Mon, 19 Feb 2024 15:36:37 +0000
-Subject: [PATCH] thermal/drivers/sun8i: Add SRAM register access code
-
-The Allwinner H616 SoC needs to clear a bit in one register in the SRAM
-controller, to report reasonable temperature values. On reset, bit 16 in
-register 0x3000000 is set, which leads to the driver reporting
-temperatures around 200C. Clearing this bit brings the values down to the
-expected range. The BSP code does a one-time write in U-Boot, with a
-comment just mentioning the effect on the THS, but offering no further
-explanation.
-
-To not rely on firmware to set things up for us, add code that queries
-the SRAM controller device via a DT phandle link, then clear just this
-single bit.
-
-Signed-off-by: Andre Przywara <andre.przywara@arm.com>
-Acked-by: Vasily Khoruzhick <anarsoul@gmail.com>
-Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
-Link: https://lore.kernel.org/r/20240219153639.179814-6-andre.przywara@arm.com
----
- drivers/thermal/sun8i_thermal.c | 51 +++++++++++++++++++++++++++++++++
- 1 file changed, 51 insertions(+)
-
---- a/drivers/thermal/sun8i_thermal.c
-+++ b/drivers/thermal/sun8i_thermal.c
-@@ -15,6 +15,7 @@
- #include <linux/module.h>
- #include <linux/nvmem-consumer.h>
- #include <linux/of.h>
-+#include <linux/of_platform.h>
- #include <linux/platform_device.h>
- #include <linux/regmap.h>
- #include <linux/reset.h>
-@@ -66,6 +67,7 @@ struct tsensor {
- struct ths_thermal_chip {
- bool has_mod_clk;
- bool has_bus_clk_reset;
-+ bool needs_sram;
- int sensor_num;
- int offset;
- int scale;
-@@ -83,12 +85,16 @@ struct ths_device {
- const struct ths_thermal_chip *chip;
- struct device *dev;
- struct regmap *regmap;
-+ struct regmap_field *sram_regmap_field;
- struct reset_control *reset;
- struct clk *bus_clk;
- struct clk *mod_clk;
- struct tsensor sensor[MAX_SENSOR_NUM];
- };
-
-+/* The H616 needs to have a bit 16 in the SRAM control register cleared. */
-+static const struct reg_field sun8i_ths_sram_reg_field = REG_FIELD(0x0, 16, 16);
-+
- /* Temp Unit: millidegree Celsius */
- static int sun8i_ths_calc_temp(struct ths_device *tmdev,
- int id, int reg)
-@@ -337,6 +343,34 @@ static void sun8i_ths_reset_control_asse
- reset_control_assert(data);
- }
-
-+static struct regmap *sun8i_ths_get_sram_regmap(struct device_node *node)
-+{
-+ struct device_node *sram_node;
-+ struct platform_device *sram_pdev;
-+ struct regmap *regmap = NULL;
-+
-+ sram_node = of_parse_phandle(node, "allwinner,sram", 0);
-+ if (!sram_node)
-+ return ERR_PTR(-ENODEV);
-+
-+ sram_pdev = of_find_device_by_node(sram_node);
-+ if (!sram_pdev) {
-+ /* platform device might not be probed yet */
-+ regmap = ERR_PTR(-EPROBE_DEFER);
-+ goto out_put_node;
-+ }
-+
-+ /* If no regmap is found then the other device driver is at fault */
-+ regmap = dev_get_regmap(&sram_pdev->dev, NULL);
-+ if (!regmap)
-+ regmap = ERR_PTR(-EINVAL);
-+
-+ platform_device_put(sram_pdev);
-+out_put_node:
-+ of_node_put(sram_node);
-+ return regmap;
-+}
-+
- static int sun8i_ths_resource_init(struct ths_device *tmdev)
- {
- struct device *dev = tmdev->dev;
-@@ -381,6 +415,19 @@ static int sun8i_ths_resource_init(struc
- if (ret)
- return ret;
-
-+ if (tmdev->chip->needs_sram) {
-+ struct regmap *regmap;
-+
-+ regmap = sun8i_ths_get_sram_regmap(dev->of_node);
-+ if (IS_ERR(regmap))
-+ return PTR_ERR(regmap);
-+ tmdev->sram_regmap_field = devm_regmap_field_alloc(dev,
-+ regmap,
-+ sun8i_ths_sram_reg_field);
-+ if (IS_ERR(tmdev->sram_regmap_field))
-+ return PTR_ERR(tmdev->sram_regmap_field);
-+ }
-+
- ret = sun8i_ths_calibrate(tmdev);
- if (ret)
- return ret;
-@@ -427,6 +474,10 @@ static int sun50i_h6_thermal_init(struct
- {
- int val;
-
-+ /* The H616 needs to have a bit in the SRAM control register cleared. */
-+ if (tmdev->sram_regmap_field)
-+ regmap_field_write(tmdev->sram_regmap_field, 0);
-+
- /*
- * The manual recommends an overall sample frequency of 50 KHz (20us,
- * 480 cycles at 24 MHz), which provides plenty of time for both the
+++ /dev/null
-From e7dbfa19572a1440a2e67ef70f94ff204849a0a8 Mon Sep 17 00:00:00 2001
-From: Martin Botka <martin.botka@somainline.org>
-Date: Mon, 19 Feb 2024 15:36:38 +0000
-Subject: [PATCH] thermal/drivers/sun8i: Add support for H616 THS controller
-
-Add support for the thermal sensor found in H616 SoCs, is the same as
-the H6 thermal sensor controller, but with four sensors.
-Also the registers readings are wrong, unless a bit in the first SYS_CFG
-register cleared, so set exercise the SRAM regmap to take care of that.
-
-Signed-off-by: Martin Botka <martin.botka@somainline.org>
-Signed-off-by: Andre Przywara <andre.przywara@arm.com>
-Acked-by: Vasily Khoruzhick <anarsoul@gmail.com>
-Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
-Link: https://lore.kernel.org/r/20240219153639.179814-7-andre.przywara@arm.com
----
- drivers/thermal/sun8i_thermal.c | 15 +++++++++++++++
- 1 file changed, 15 insertions(+)
-
---- a/drivers/thermal/sun8i_thermal.c
-+++ b/drivers/thermal/sun8i_thermal.c
-@@ -684,6 +684,20 @@ static const struct ths_thermal_chip sun
- .calc_temp = sun8i_ths_calc_temp,
- };
-
-+static const struct ths_thermal_chip sun50i_h616_ths = {
-+ .sensor_num = 4,
-+ .has_bus_clk_reset = true,
-+ .needs_sram = true,
-+ .ft_deviation = 8000,
-+ .offset = 263655,
-+ .scale = 810,
-+ .temp_data_base = SUN50I_H6_THS_TEMP_DATA,
-+ .calibrate = sun50i_h6_ths_calibrate,
-+ .init = sun50i_h6_thermal_init,
-+ .irq_ack = sun50i_h6_irq_ack,
-+ .calc_temp = sun8i_ths_calc_temp,
-+};
-+
- static const struct of_device_id of_ths_match[] = {
- { .compatible = "allwinner,sun8i-a83t-ths", .data = &sun8i_a83t_ths },
- { .compatible = "allwinner,sun8i-h3-ths", .data = &sun8i_h3_ths },
-@@ -693,6 +707,7 @@ static const struct of_device_id of_ths_
- { .compatible = "allwinner,sun50i-h5-ths", .data = &sun50i_h5_ths },
- { .compatible = "allwinner,sun50i-h6-ths", .data = &sun50i_h6_ths },
- { .compatible = "allwinner,sun20i-d1-ths", .data = &sun20i_d1_ths },
-+ { .compatible = "allwinner,sun50i-h616-ths", .data = &sun50i_h616_ths },
- { /* sentinel */ },
- };
- MODULE_DEVICE_TABLE(of, of_ths_match);
+++ /dev/null
-From 9ac53d5532cc4bb595bbee86ccba2172ccc336c3 Mon Sep 17 00:00:00 2001
-From: Mark Brown <broonie@kernel.org>
-Date: Tue, 23 Jan 2024 23:33:07 +0000
-Subject: [PATCH] thermal/drivers/sun8i: Don't fail probe due to zone
- registration failure
-
-Currently the sun8i thermal driver will fail to probe if any of the
-thermal zones it is registering fails to register with the thermal core.
-Since we currently do not define any trip points for the GPU thermal
-zones on at least A64 or H5 this means that we have no thermal support
-on these platforms:
-
-[ 1.698703] thermal_sys: Failed to find 'trips' node
-[ 1.698707] thermal_sys: Failed to find trip points for thermal-sensor id=1
-
-even though the main CPU thermal zone on both SoCs is fully configured.
-This does not seem ideal, while we may not be able to use all the zones
-it seems better to have those zones which are usable be operational.
-Instead just carry on registering zones if we get any non-deferral
-error, allowing use of those zones which are usable.
-
-This means that we also need to update the interrupt handler to not
-attempt to notify the core for events on zones which we have not
-registered, I didn't see an ability to mask individual interrupts and
-I would expect that interrupts would still be indicated in the ISR even
-if they were masked.
-
-Reviewed-by: Vasily Khoruzhick <anarsoul@gmail.com>
-Acked-by: Jernej Skrabec <jernej.skrabec@gmail.com>
-Signed-off-by: Mark Brown <broonie@kernel.org>
-Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
-Link: https://lore.kernel.org/r/20240123-thermal-sun8i-registration-v3-1-3e5771b1bbdd@kernel.org
----
- drivers/thermal/sun8i_thermal.c | 16 ++++++++++++++--
- 1 file changed, 14 insertions(+), 2 deletions(-)
-
---- a/drivers/thermal/sun8i_thermal.c
-+++ b/drivers/thermal/sun8i_thermal.c
-@@ -195,6 +195,9 @@ static irqreturn_t sun8i_irq_thread(int
- int i;
-
- for_each_set_bit(i, &irq_bitmap, tmdev->chip->sensor_num) {
-+ /* We allow some zones to not register. */
-+ if (IS_ERR(tmdev->sensor[i].tzd))
-+ continue;
- thermal_zone_device_update(tmdev->sensor[i].tzd,
- THERMAL_EVENT_UNSPECIFIED);
- }
-@@ -531,8 +534,17 @@ static int sun8i_ths_register(struct ths
- i,
- &tmdev->sensor[i],
- &ths_ops);
-- if (IS_ERR(tmdev->sensor[i].tzd))
-- return PTR_ERR(tmdev->sensor[i].tzd);
-+
-+ /*
-+ * If an individual zone fails to register for reasons
-+ * other than probe deferral (eg, a bad DT) then carry
-+ * on, other zones might register successfully.
-+ */
-+ if (IS_ERR(tmdev->sensor[i].tzd)) {
-+ if (PTR_ERR(tmdev->sensor[i].tzd) == -EPROBE_DEFER)
-+ return PTR_ERR(tmdev->sensor[i].tzd);
-+ continue;
-+ }
-
- devm_thermal_add_hwmon_sysfs(tmdev->dev, tmdev->sensor[i].tzd);
- }
+++ /dev/null
-From f4318af40544b8e7ff5a6b667ede60e6cf808262 Mon Sep 17 00:00:00 2001
-From: Martin Botka <martin.botka@somainline.org>
-Date: Mon, 19 Feb 2024 15:36:39 +0000
-Subject: [PATCH] arm64: dts: allwinner: h616: Add thermal sensor and zones
-
-There are four thermal sensors:
-- CPU
-- GPU
-- VE
-- DRAM
-
-Add the thermal sensor configuration and the thermal zones.
-
-Signed-off-by: Martin Botka <martin.botka@somainline.org>
-Signed-off-by: Andre Przywara <andre.przywara@arm.com>
-Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com>
-Link: https://lore.kernel.org/r/20240219153639.179814-8-andre.przywara@arm.com
-Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
----
- .../arm64/boot/dts/allwinner/sun50i-h616.dtsi | 88 +++++++++++++++++++
- 1 file changed, 88 insertions(+)
-
---- a/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi
-+++ b/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi
-@@ -9,6 +9,7 @@
- #include <dt-bindings/clock/sun6i-rtc.h>
- #include <dt-bindings/reset/sun50i-h616-ccu.h>
- #include <dt-bindings/reset/sun50i-h6-r-ccu.h>
-+#include <dt-bindings/thermal/thermal.h>
-
- / {
- interrupt-parent = <&gic>;
-@@ -138,6 +139,10 @@
- reg = <0x03006000 0x1000>;
- #address-cells = <1>;
- #size-cells = <1>;
-+
-+ ths_calibration: thermal-sensor-calibration@14 {
-+ reg = <0x14 0x8>;
-+ };
- };
-
- watchdog: watchdog@30090a0 {
-@@ -511,6 +516,19 @@
- };
- };
-
-+ ths: thermal-sensor@5070400 {
-+ compatible = "allwinner,sun50i-h616-ths";
-+ reg = <0x05070400 0x400>;
-+ interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
-+ clocks = <&ccu CLK_BUS_THS>;
-+ clock-names = "bus";
-+ resets = <&ccu RST_BUS_THS>;
-+ nvmem-cells = <&ths_calibration>;
-+ nvmem-cell-names = "calibration";
-+ allwinner,sram = <&syscon>;
-+ #thermal-sensor-cells = <1>;
-+ };
-+
- usbotg: usb@5100000 {
- compatible = "allwinner,sun50i-h616-musb",
- "allwinner,sun8i-h3-musb";
-@@ -755,4 +773,74 @@
- #size-cells = <0>;
- };
- };
-+
-+ thermal-zones {
-+ cpu-thermal {
-+ polling-delay-passive = <500>;
-+ polling-delay = <1000>;
-+ thermal-sensors = <&ths 2>;
-+ sustainable-power = <1000>;
-+
-+ trips {
-+ cpu_threshold: cpu-trip-0 {
-+ temperature = <60000>;
-+ type = "passive";
-+ hysteresis = <0>;
-+ };
-+ cpu_target: cpu-trip-1 {
-+ temperature = <70000>;
-+ type = "passive";
-+ hysteresis = <0>;
-+ };
-+ cpu_critical: cpu-trip-2 {
-+ temperature = <110000>;
-+ type = "critical";
-+ hysteresis = <0>;
-+ };
-+ };
-+ };
-+
-+ gpu-thermal {
-+ polling-delay-passive = <500>;
-+ polling-delay = <1000>;
-+ thermal-sensors = <&ths 0>;
-+ sustainable-power = <1100>;
-+
-+ trips {
-+ gpu_temp_critical: gpu-trip-0 {
-+ temperature = <110000>;
-+ type = "critical";
-+ hysteresis = <0>;
-+ };
-+ };
-+ };
-+
-+ ve-thermal {
-+ polling-delay-passive = <0>;
-+ polling-delay = <0>;
-+ thermal-sensors = <&ths 1>;
-+
-+ trips {
-+ ve_temp_critical: ve-trip-0 {
-+ temperature = <110000>;
-+ type = "critical";
-+ hysteresis = <0>;
-+ };
-+ };
-+ };
-+
-+ ddr-thermal {
-+ polling-delay-passive = <0>;
-+ polling-delay = <0>;
-+ thermal-sensors = <&ths 3>;
-+
-+ trips {
-+ ddr_temp_critical: ddr-trip-0 {
-+ temperature = <110000>;
-+ type = "critical";
-+ hysteresis = <0>;
-+ };
-+ };
-+ };
-+ };
- };
+++ /dev/null
-From 9cf3415ade2d7598d78d2ce6d35d6d6d06132201 Mon Sep 17 00:00:00 2001
-From: Martin Botka <martin.botka@somainline.org>
-Date: Thu, 18 Apr 2024 16:44:01 +0100
-Subject: [PATCH] firmware: smccc: Export revision soc_id function
-
-The "SoC ID revision" as provided via the SMCCC SOCID interface can be
-valuable information for drivers, when certain functionality depends
-on a die revision, for instance.
-One example is the sun50i-cpufreq-nvmem driver, which needs this
-information to determine the speed bin of the SoC.
-
-Export the arm_smccc_get_soc_id_revision() function so that it can be
-called by any driver.
-
-Signed-off-by: Martin Botka <martin.botka@somainline.org>
-Signed-off-by: Andre Przywara <andre.przywara@arm.com>
-Acked-by: Sudeep Holla <sudeep.holla@arm.com>
-Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
----
- drivers/firmware/smccc/smccc.c | 1 +
- 1 file changed, 1 insertion(+)
-
---- a/drivers/firmware/smccc/smccc.c
-+++ b/drivers/firmware/smccc/smccc.c
-@@ -65,6 +65,7 @@ s32 arm_smccc_get_soc_id_revision(void)
- {
- return smccc_soc_id_revision;
- }
-+EXPORT_SYMBOL_GPL(arm_smccc_get_soc_id_revision);
-
- static int __init smccc_devices_init(void)
- {
+++ /dev/null
-From 6ae07744cf334b750762ba881492c0cfba524b38 Mon Sep 17 00:00:00 2001
-From: Martin Botka <martin.botka@somainline.org>
-Date: Thu, 18 Apr 2024 16:44:02 +0100
-Subject: [PATCH] cpufreq: dt-platdev: Blocklist Allwinner H616/618 SoCs
-
-The AllWinner H616 SoC will use the (extended) H6 OPP driver, so add
-them to the cpufreq-dt blocklist, to not create the device twice.
-This also affects the closely related sibling SoCs H618 and H700.
-
-Signed-off-by: Martin Botka <martin.botka@somainline.org>
-Signed-off-by: Andre Przywara <andre.przywara@arm.com>
-Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com>
-Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
----
- drivers/cpufreq/cpufreq-dt-platdev.c | 3 +++
- 1 file changed, 3 insertions(+)
-
---- a/drivers/cpufreq/cpufreq-dt-platdev.c
-+++ b/drivers/cpufreq/cpufreq-dt-platdev.c
-@@ -104,6 +104,9 @@ static const struct of_device_id allowli
- */
- static const struct of_device_id blocklist[] __initconst = {
- { .compatible = "allwinner,sun50i-h6", },
-+ { .compatible = "allwinner,sun50i-h616", },
-+ { .compatible = "allwinner,sun50i-h618", },
-+ { .compatible = "allwinner,sun50i-h700", },
-
- { .compatible = "apple,arm-platform", },
-
+++ /dev/null
-From 6cc4bcceff9af0e6be9738096d95e4ba75e75123 Mon Sep 17 00:00:00 2001
-From: Brandon Cheo Fusi <fusibrandon13@gmail.com>
-Date: Thu, 18 Apr 2024 16:44:04 +0100
-Subject: [PATCH] cpufreq: sun50i: Refactor speed bin decoding
-
-Make converting the speed bin value into a speed grade generic and
-determined by a platform specific callback. Also change the prototypes
-involved to encode the speed bin directly in the return value.
-
-This allows to extend the driver more easily to support more SoCs.
-
-Signed-off-by: Brandon Cheo Fusi <fusibrandon13@gmail.com>
-[Andre: merge output into return value]
-Signed-off-by: Andre Przywara <andre.przywara@arm.com>
-Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com>
-Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
----
- drivers/cpufreq/sun50i-cpufreq-nvmem.c | 74 +++++++++++++++++---------
- 1 file changed, 49 insertions(+), 25 deletions(-)
-
---- a/drivers/cpufreq/sun50i-cpufreq-nvmem.c
-+++ b/drivers/cpufreq/sun50i-cpufreq-nvmem.c
-@@ -25,19 +25,52 @@
-
- static struct platform_device *cpufreq_dt_pdev, *sun50i_cpufreq_pdev;
-
-+struct sunxi_cpufreq_data {
-+ u32 (*efuse_xlate)(u32 speedbin);
-+};
-+
-+static u32 sun50i_h6_efuse_xlate(u32 speedbin)
-+{
-+ u32 efuse_value;
-+
-+ efuse_value = (speedbin >> NVMEM_SHIFT) & NVMEM_MASK;
-+
-+ /*
-+ * We treat unexpected efuse values as if the SoC was from
-+ * the slowest bin. Expected efuse values are 1-3, slowest
-+ * to fastest.
-+ */
-+ if (efuse_value >= 1 && efuse_value <= 3)
-+ return efuse_value - 1;
-+ else
-+ return 0;
-+}
-+
-+static struct sunxi_cpufreq_data sun50i_h6_cpufreq_data = {
-+ .efuse_xlate = sun50i_h6_efuse_xlate,
-+};
-+
-+static const struct of_device_id cpu_opp_match_list[] = {
-+ { .compatible = "allwinner,sun50i-h6-operating-points",
-+ .data = &sun50i_h6_cpufreq_data,
-+ },
-+ {}
-+};
-+
- /**
- * sun50i_cpufreq_get_efuse() - Determine speed grade from efuse value
-- * @versions: Set to the value parsed from efuse
- *
-- * Returns 0 if success.
-+ * Returns non-negative speed bin index on success, a negative error
-+ * value otherwise.
- */
--static int sun50i_cpufreq_get_efuse(u32 *versions)
-+static int sun50i_cpufreq_get_efuse(void)
- {
-+ const struct sunxi_cpufreq_data *opp_data;
- struct nvmem_cell *speedbin_nvmem;
-+ const struct of_device_id *match;
- struct device_node *np;
- struct device *cpu_dev;
-- u32 *speedbin, efuse_value;
-- size_t len;
-+ u32 *speedbin;
- int ret;
-
- cpu_dev = get_cpu_device(0);
-@@ -48,12 +81,12 @@ static int sun50i_cpufreq_get_efuse(u32
- if (!np)
- return -ENOENT;
-
-- ret = of_device_is_compatible(np,
-- "allwinner,sun50i-h6-operating-points");
-- if (!ret) {
-+ match = of_match_node(cpu_opp_match_list, np);
-+ if (!match) {
- of_node_put(np);
- return -ENOENT;
- }
-+ opp_data = match->data;
-
- speedbin_nvmem = of_nvmem_cell_get(np, NULL);
- of_node_put(np);
-@@ -61,25 +94,16 @@ static int sun50i_cpufreq_get_efuse(u32
- return dev_err_probe(cpu_dev, PTR_ERR(speedbin_nvmem),
- "Could not get nvmem cell\n");
-
-- speedbin = nvmem_cell_read(speedbin_nvmem, &len);
-+ speedbin = nvmem_cell_read(speedbin_nvmem, NULL);
- nvmem_cell_put(speedbin_nvmem);
- if (IS_ERR(speedbin))
- return PTR_ERR(speedbin);
-
-- efuse_value = (*speedbin >> NVMEM_SHIFT) & NVMEM_MASK;
--
-- /*
-- * We treat unexpected efuse values as if the SoC was from
-- * the slowest bin. Expected efuse values are 1-3, slowest
-- * to fastest.
-- */
-- if (efuse_value >= 1 && efuse_value <= 3)
-- *versions = efuse_value - 1;
-- else
-- *versions = 0;
-+ ret = opp_data->efuse_xlate(*speedbin);
-
- kfree(speedbin);
-- return 0;
-+
-+ return ret;
- };
-
- static int sun50i_cpufreq_nvmem_probe(struct platform_device *pdev)
-@@ -87,7 +111,7 @@ static int sun50i_cpufreq_nvmem_probe(st
- int *opp_tokens;
- char name[MAX_NAME_LEN];
- unsigned int cpu;
-- u32 speed = 0;
-+ int speed;
- int ret;
-
- opp_tokens = kcalloc(num_possible_cpus(), sizeof(*opp_tokens),
-@@ -95,10 +119,10 @@ static int sun50i_cpufreq_nvmem_probe(st
- if (!opp_tokens)
- return -ENOMEM;
-
-- ret = sun50i_cpufreq_get_efuse(&speed);
-- if (ret) {
-+ speed = sun50i_cpufreq_get_efuse();
-+ if (speed < 0) {
- kfree(opp_tokens);
-- return ret;
-+ return speed;
- }
-
- snprintf(name, MAX_NAME_LEN, "speed%d", speed);
+++ /dev/null
-From fa5aec9561cfc4f4370983ca5818c90227c9d90e Mon Sep 17 00:00:00 2001
-From: Andre Przywara <andre.przywara@arm.com>
-Date: Thu, 18 Apr 2024 16:44:05 +0100
-Subject: [PATCH] cpufreq: sun50i: Add support for opp_supported_hw
-
-The opp_supported_hw DT property allows the DT to specify a mask of chip
-revisions that a certain OPP is eligible for. This allows for easy
-limiting of maximum frequencies, for instance.
-
-Add support for that in the sun50i-cpufreq-nvmem driver. We support both
-the existing opp-microvolt suffix properties as well as the
-opp-supported-hw property, the generic code figures out which is needed
-automatically.
-However if none of the DT OPP nodes contain an opp-supported-hw
-property, the core code will ignore all OPPs and the driver will fail
-probing. So check the DT's eligibility first before using that feature.
-
-Signed-off-by: Andre Przywara <andre.przywara@arm.com>
-Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com>
-Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
----
- drivers/cpufreq/sun50i-cpufreq-nvmem.c | 62 ++++++++++++++++++++++----
- 1 file changed, 54 insertions(+), 8 deletions(-)
-
---- a/drivers/cpufreq/sun50i-cpufreq-nvmem.c
-+++ b/drivers/cpufreq/sun50i-cpufreq-nvmem.c
-@@ -58,6 +58,41 @@ static const struct of_device_id cpu_opp
- };
-
- /**
-+ * dt_has_supported_hw() - Check if any OPPs use opp-supported-hw
-+ *
-+ * If we ask the cpufreq framework to use the opp-supported-hw feature, it
-+ * will ignore every OPP node without that DT property. If none of the OPPs
-+ * have it, the driver will fail probing, due to the lack of OPPs.
-+ *
-+ * Returns true if we have at least one OPP with the opp-supported-hw property.
-+ */
-+static bool dt_has_supported_hw(void)
-+{
-+ bool has_opp_supported_hw = false;
-+ struct device_node *np, *opp;
-+ struct device *cpu_dev;
-+
-+ cpu_dev = get_cpu_device(0);
-+ if (!cpu_dev)
-+ return -ENODEV;
-+
-+ np = dev_pm_opp_of_get_opp_desc_node(cpu_dev);
-+ if (!np)
-+ return -ENOENT;
-+
-+ for_each_child_of_node(np, opp) {
-+ if (of_find_property(opp, "opp-supported-hw", NULL)) {
-+ has_opp_supported_hw = true;
-+ break;
-+ }
-+ }
-+
-+ of_node_put(np);
-+
-+ return has_opp_supported_hw;
-+}
-+
-+/**
- * sun50i_cpufreq_get_efuse() - Determine speed grade from efuse value
- *
- * Returns non-negative speed bin index on success, a negative error
-@@ -110,7 +145,8 @@ static int sun50i_cpufreq_nvmem_probe(st
- {
- int *opp_tokens;
- char name[MAX_NAME_LEN];
-- unsigned int cpu;
-+ unsigned int cpu, supported_hw;
-+ struct dev_pm_opp_config config = {};
- int speed;
- int ret;
-
-@@ -125,7 +161,18 @@ static int sun50i_cpufreq_nvmem_probe(st
- return speed;
- }
-
-+ /*
-+ * We need at least one OPP with the "opp-supported-hw" property,
-+ * or else the upper layers will ignore every OPP and will bail out.
-+ */
-+ if (dt_has_supported_hw()) {
-+ supported_hw = 1U << speed;
-+ config.supported_hw = &supported_hw;
-+ config.supported_hw_count = 1;
-+ }
-+
- snprintf(name, MAX_NAME_LEN, "speed%d", speed);
-+ config.prop_name = name;
-
- for_each_possible_cpu(cpu) {
- struct device *cpu_dev = get_cpu_device(cpu);
-@@ -135,12 +182,11 @@ static int sun50i_cpufreq_nvmem_probe(st
- goto free_opp;
- }
-
-- opp_tokens[cpu] = dev_pm_opp_set_prop_name(cpu_dev, name);
-- if (opp_tokens[cpu] < 0) {
-- ret = opp_tokens[cpu];
-- pr_err("Failed to set prop name\n");
-+ ret = dev_pm_opp_set_config(cpu_dev, &config);
-+ if (ret < 0)
- goto free_opp;
-- }
-+
-+ opp_tokens[cpu] = ret;
- }
-
- cpufreq_dt_pdev = platform_device_register_simple("cpufreq-dt", -1,
-@@ -155,7 +201,7 @@ static int sun50i_cpufreq_nvmem_probe(st
-
- free_opp:
- for_each_possible_cpu(cpu)
-- dev_pm_opp_put_prop_name(opp_tokens[cpu]);
-+ dev_pm_opp_clear_config(opp_tokens[cpu]);
- kfree(opp_tokens);
-
- return ret;
-@@ -169,7 +215,7 @@ static void sun50i_cpufreq_nvmem_remove(
- platform_device_unregister(cpufreq_dt_pdev);
-
- for_each_possible_cpu(cpu)
-- dev_pm_opp_put_prop_name(opp_tokens[cpu]);
-+ dev_pm_opp_clear_config(opp_tokens[cpu]);
-
- kfree(opp_tokens);
- }
+++ /dev/null
-From e2e2dcd2e944fe6167cb731864f8a1343f1bbee7 Mon Sep 17 00:00:00 2001
-From: Martin Botka <martin.botka@somainline.org>
-Date: Thu, 18 Apr 2024 16:44:06 +0100
-Subject: [PATCH] cpufreq: sun50i: Add H616 support
-
-The Allwinner H616/H618 SoCs have different OPP tables per SoC version
-and die revision. The SoC version is stored in NVMEM, as before, though
-encoded differently. The die revision is in a different register, in the
-SRAM controller. Firmware already exports that value in a standardised
-way, through the SMCCC SoCID mechanism. We need both values, as some chips
-have the same SoC version, but they don't support the same frequencies and
-they get differentiated by the die revision.
-
-Add the new compatible string and tie the new translation function to
-it. This mechanism not only covers the original H616 SoC, but also its
-very close sibling SoCs H618 and H700, so add them to the list as well.
-
-Signed-off-by: Martin Botka <martin.botka@somainline.org>
-Signed-off-by: Andre Przywara <andre.przywara@arm.com>
-Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
----
- drivers/cpufreq/sun50i-cpufreq-nvmem.c | 67 ++++++++++++++++++++++++++
- 1 file changed, 67 insertions(+)
-
---- a/drivers/cpufreq/sun50i-cpufreq-nvmem.c
-+++ b/drivers/cpufreq/sun50i-cpufreq-nvmem.c
-@@ -10,6 +10,7 @@
-
- #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
-
-+#include <linux/arm-smccc.h>
- #include <linux/cpu.h>
- #include <linux/module.h>
- #include <linux/nvmem-consumer.h>
-@@ -46,14 +47,77 @@ static u32 sun50i_h6_efuse_xlate(u32 spe
- return 0;
- }
-
-+static int get_soc_id_revision(void)
-+{
-+#ifdef CONFIG_HAVE_ARM_SMCCC_DISCOVERY
-+ return arm_smccc_get_soc_id_revision();
-+#else
-+ return SMCCC_RET_NOT_SUPPORTED;
-+#endif
-+}
-+
-+/*
-+ * Judging by the OPP tables in the vendor BSP, the quality order of the
-+ * returned speedbin index is 4 -> 0/2 -> 3 -> 1, from worst to best.
-+ * 0 and 2 seem identical from the OPP tables' point of view.
-+ */
-+static u32 sun50i_h616_efuse_xlate(u32 speedbin)
-+{
-+ int ver_bits = get_soc_id_revision();
-+ u32 value = 0;
-+
-+ switch (speedbin & 0xffff) {
-+ case 0x2000:
-+ value = 0;
-+ break;
-+ case 0x2400:
-+ case 0x7400:
-+ case 0x2c00:
-+ case 0x7c00:
-+ if (ver_bits != SMCCC_RET_NOT_SUPPORTED && ver_bits <= 1) {
-+ /* ic version A/B */
-+ value = 1;
-+ } else {
-+ /* ic version C and later version */
-+ value = 2;
-+ }
-+ break;
-+ case 0x5000:
-+ case 0x5400:
-+ case 0x6000:
-+ value = 3;
-+ break;
-+ case 0x5c00:
-+ value = 4;
-+ break;
-+ case 0x5d00:
-+ value = 0;
-+ break;
-+ default:
-+ pr_warn("sun50i-cpufreq-nvmem: unknown speed bin 0x%x, using default bin 0\n",
-+ speedbin & 0xffff);
-+ value = 0;
-+ break;
-+ }
-+
-+ return value;
-+}
-+
- static struct sunxi_cpufreq_data sun50i_h6_cpufreq_data = {
- .efuse_xlate = sun50i_h6_efuse_xlate,
- };
-
-+static struct sunxi_cpufreq_data sun50i_h616_cpufreq_data = {
-+ .efuse_xlate = sun50i_h616_efuse_xlate,
-+};
-+
- static const struct of_device_id cpu_opp_match_list[] = {
- { .compatible = "allwinner,sun50i-h6-operating-points",
- .data = &sun50i_h6_cpufreq_data,
- },
-+ { .compatible = "allwinner,sun50i-h616-operating-points",
-+ .data = &sun50i_h616_cpufreq_data,
-+ },
- {}
- };
-
-@@ -230,6 +294,9 @@ static struct platform_driver sun50i_cpu
-
- static const struct of_device_id sun50i_cpufreq_match_list[] = {
- { .compatible = "allwinner,sun50i-h6" },
-+ { .compatible = "allwinner,sun50i-h616" },
-+ { .compatible = "allwinner,sun50i-h618" },
-+ { .compatible = "allwinner,sun50i-h700" },
- {}
- };
- MODULE_DEVICE_TABLE(of, sun50i_cpufreq_match_list);
+++ /dev/null
-From 3e057e05b3b281bcc29db573eb51f87ee6b5afc0 Mon Sep 17 00:00:00 2001
-From: Martin Botka <martin.botka@somainline.org>
-Date: Thu, 18 Apr 2024 16:44:07 +0100
-Subject: [PATCH] arm64: dts: allwinner: h616: Add CPU OPPs table
-
-Add an Operating Performance Points table for the CPU cores to enable
-Dynamic Voltage & Frequency Scaling (DVFS) on the H616.
-The values were taken from the BSP sources. There is a separate OPP set
-seen on some H700 devices, but they didn't really work out in testing, so
-they are not included for now.
-
-Also add the needed cpu_speed_grade nvmem cell and the cooling cells
-properties, to enable passive cooling.
-
-Signed-off-by: Martin Botka <martin.botka@somainline.org>
-[Andre: rework to minimise opp-microvolt properties]
-Signed-off-by: Andre Przywara <andre.przywara@arm.com>
-Acked-by: Jernej Skrabec <jernej.skrabec@gmail.com>
-Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
----
- .../dts/allwinner/sun50i-h616-cpu-opp.dtsi | 115 ++++++++++++++++++
- .../arm64/boot/dts/allwinner/sun50i-h616.dtsi | 8 ++
- 2 files changed, 123 insertions(+)
- create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-h616-cpu-opp.dtsi
-
---- /dev/null
-+++ b/arch/arm64/boot/dts/allwinner/sun50i-h616-cpu-opp.dtsi
-@@ -0,0 +1,115 @@
-+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-+// Copyright (C) 2023 Martin Botka <martin@somainline.org>
-+
-+/ {
-+ cpu_opp_table: opp-table-cpu {
-+ compatible = "allwinner,sun50i-h616-operating-points";
-+ nvmem-cells = <&cpu_speed_grade>;
-+ opp-shared;
-+
-+ opp-480000000 {
-+ opp-hz = /bits/ 64 <480000000>;
-+ opp-microvolt = <900000>;
-+ clock-latency-ns = <244144>; /* 8 32k periods */
-+ opp-supported-hw = <0x1f>;
-+ };
-+
-+ opp-600000000 {
-+ opp-hz = /bits/ 64 <600000000>;
-+ opp-microvolt = <900000>;
-+ clock-latency-ns = <244144>; /* 8 32k periods */
-+ opp-supported-hw = <0x12>;
-+ };
-+
-+ opp-720000000 {
-+ opp-hz = /bits/ 64 <720000000>;
-+ opp-microvolt = <900000>;
-+ clock-latency-ns = <244144>; /* 8 32k periods */
-+ opp-supported-hw = <0x0d>;
-+ };
-+
-+ opp-792000000 {
-+ opp-hz = /bits/ 64 <792000000>;
-+ opp-microvolt-speed1 = <900000>;
-+ opp-microvolt-speed4 = <940000>;
-+ clock-latency-ns = <244144>; /* 8 32k periods */
-+ opp-supported-hw = <0x12>;
-+ };
-+
-+ opp-936000000 {
-+ opp-hz = /bits/ 64 <936000000>;
-+ opp-microvolt = <900000>;
-+ clock-latency-ns = <244144>; /* 8 32k periods */
-+ opp-supported-hw = <0x0d>;
-+ };
-+
-+ opp-1008000000 {
-+ opp-hz = /bits/ 64 <1008000000>;
-+ opp-microvolt-speed0 = <950000>;
-+ opp-microvolt-speed1 = <940000>;
-+ opp-microvolt-speed2 = <950000>;
-+ opp-microvolt-speed3 = <950000>;
-+ opp-microvolt-speed4 = <1020000>;
-+ clock-latency-ns = <244144>; /* 8 32k periods */
-+ opp-supported-hw = <0x1f>;
-+ };
-+
-+ opp-1104000000 {
-+ opp-hz = /bits/ 64 <1104000000>;
-+ opp-microvolt-speed0 = <1000000>;
-+ opp-microvolt-speed2 = <1000000>;
-+ opp-microvolt-speed3 = <1000000>;
-+ clock-latency-ns = <244144>; /* 8 32k periods */
-+ opp-supported-hw = <0x0d>;
-+ };
-+
-+ opp-1200000000 {
-+ opp-hz = /bits/ 64 <1200000000>;
-+ opp-microvolt-speed0 = <1050000>;
-+ opp-microvolt-speed1 = <1020000>;
-+ opp-microvolt-speed2 = <1050000>;
-+ opp-microvolt-speed3 = <1050000>;
-+ opp-microvolt-speed4 = <1100000>;
-+ clock-latency-ns = <244144>; /* 8 32k periods */
-+ opp-supported-hw = <0x1f>;
-+ };
-+
-+ opp-1320000000 {
-+ opp-hz = /bits/ 64 <1320000000>;
-+ opp-microvolt = <1100000>;
-+ clock-latency-ns = <244144>; /* 8 32k periods */
-+ opp-supported-hw = <0x1d>;
-+ };
-+
-+ opp-1416000000 {
-+ opp-hz = /bits/ 64 <1416000000>;
-+ opp-microvolt = <1100000>;
-+ clock-latency-ns = <244144>; /* 8 32k periods */
-+ opp-supported-hw = <0x0d>;
-+ };
-+
-+ opp-1512000000 {
-+ opp-hz = /bits/ 64 <1512000000>;
-+ opp-microvolt-speed1 = <1100000>;
-+ opp-microvolt-speed3 = <1100000>;
-+ clock-latency-ns = <244144>; /* 8 32k periods */
-+ opp-supported-hw = <0x0a>;
-+ };
-+ };
-+};
-+
-+&cpu0 {
-+ operating-points-v2 = <&cpu_opp_table>;
-+};
-+
-+&cpu1 {
-+ operating-points-v2 = <&cpu_opp_table>;
-+};
-+
-+&cpu2 {
-+ operating-points-v2 = <&cpu_opp_table>;
-+};
-+
-+&cpu3 {
-+ operating-points-v2 = <&cpu_opp_table>;
-+};
---- a/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi
-+++ b/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi
-@@ -26,6 +26,7 @@
- reg = <0>;
- enable-method = "psci";
- clocks = <&ccu CLK_CPUX>;
-+ #cooling-cells = <2>;
- };
-
- cpu1: cpu@1 {
-@@ -34,6 +35,7 @@
- reg = <1>;
- enable-method = "psci";
- clocks = <&ccu CLK_CPUX>;
-+ #cooling-cells = <2>;
- };
-
- cpu2: cpu@2 {
-@@ -42,6 +44,7 @@
- reg = <2>;
- enable-method = "psci";
- clocks = <&ccu CLK_CPUX>;
-+ #cooling-cells = <2>;
- };
-
- cpu3: cpu@3 {
-@@ -50,6 +53,7 @@
- reg = <3>;
- enable-method = "psci";
- clocks = <&ccu CLK_CPUX>;
-+ #cooling-cells = <2>;
- };
- };
-
-@@ -143,6 +147,10 @@
- ths_calibration: thermal-sensor-calibration@14 {
- reg = <0x14 0x8>;
- };
-+
-+ cpu_speed_grade: cpu-speed-grade@0 {
-+ reg = <0x0 2>;
-+ };
- };
-
- watchdog: watchdog@30090a0 {
+++ /dev/null
-From 09d0aaa0ae9c80ff9569393b206226c1008801b1 Mon Sep 17 00:00:00 2001
-From: Andre Przywara <andre.przywara@arm.com>
-Date: Thu, 18 Apr 2024 16:44:08 +0100
-Subject: [PATCH] arm64: dts: allwinner: h616: enable DVFS for all boards
-
-With the DT bindings now describing the format of the CPU OPP tables, we
-can include the OPP table in each board's .dts file, and specify the CPU
-power supply.
-This allows to enable DVFS, and get up to 50% of performance benefit in
-the highest OPP, or up to 60% power savings in the lowest OPP, compared
-to the fixed 1GHz @ 1.0V OPP we are running in by default at the moment.
-
-Signed-off-by: Andre Przywara <andre.przywara@arm.com>
-Acked-by: Jernej Skrabec <jernej.skrabec@gmail.com>
-Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
----
- .../boot/dts/allwinner/sun50i-h616-bigtreetech-cb1.dtsi | 5 +++++
- arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero2.dts | 5 +++++
- arch/arm64/boot/dts/allwinner/sun50i-h616-x96-mate.dts | 5 +++++
- .../boot/dts/allwinner/sun50i-h618-longan-module-3h.dtsi | 5 +++++
- .../arm64/boot/dts/allwinner/sun50i-h618-orangepi-zero2w.dts | 5 +++++
- arch/arm64/boot/dts/allwinner/sun50i-h618-orangepi-zero3.dts | 5 +++++
- .../boot/dts/allwinner/sun50i-h618-transpeed-8k618-t.dts | 5 +++++
- 7 files changed, 35 insertions(+)
-
---- a/arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero2.dts
-+++ b/arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero2.dts
-@@ -6,12 +6,17 @@
- /dts-v1/;
-
- #include "sun50i-h616-orangepi-zero.dtsi"
-+#include "sun50i-h616-cpu-opp.dtsi"
-
- / {
- model = "OrangePi Zero2";
- compatible = "xunlong,orangepi-zero2", "allwinner,sun50i-h616";
- };
-
-+&cpu0 {
-+ cpu-supply = <®_dcdca>;
-+};
-+
- &emac0 {
- allwinner,rx-delay-ps = <3100>;
- allwinner,tx-delay-ps = <700>;
---- a/arch/arm64/boot/dts/allwinner/sun50i-h616-x96-mate.dts
-+++ b/arch/arm64/boot/dts/allwinner/sun50i-h616-x96-mate.dts
-@@ -6,6 +6,7 @@
- /dts-v1/;
-
- #include "sun50i-h616.dtsi"
-+#include "sun50i-h616-cpu-opp.dtsi"
-
- #include <dt-bindings/gpio/gpio.h>
- #include <dt-bindings/interrupt-controller/arm-gic.h>
-@@ -32,6 +33,10 @@
- };
- };
-
-+&cpu0 {
-+ cpu-supply = <®_dcdca>;
-+};
-+
- &ehci0 {
- status = "okay";
- };
---- a/arch/arm64/boot/dts/allwinner/sun50i-h618-orangepi-zero3.dts
-+++ b/arch/arm64/boot/dts/allwinner/sun50i-h618-orangepi-zero3.dts
-@@ -6,12 +6,17 @@
- /dts-v1/;
-
- #include "sun50i-h616-orangepi-zero.dtsi"
-+#include "sun50i-h616-cpu-opp.dtsi"
-
- / {
- model = "OrangePi Zero3";
- compatible = "xunlong,orangepi-zero3", "allwinner,sun50i-h618";
- };
-
-+&cpu0 {
-+ cpu-supply = <®_dcdc2>;
-+};
-+
- &emac0 {
- allwinner,tx-delay-ps = <700>;
- phy-mode = "rgmii-rxid";
+++ /dev/null
-From d2059d3b548409905b20b4f52495bffbd7c8da8b Mon Sep 17 00:00:00 2001
-From: Viresh Kumar <viresh.kumar@linaro.org>
-Date: Mon, 22 Apr 2024 08:58:51 +0530
-Subject: [PATCH] cpufreq: sun50i: Fix build warning around snprint()
-
-The Sun50i driver generates a warning with W=1:
-
-warning: '%d' directive output may be truncated writing between 1 and 10 bytes into a region of size 2 [-Wformat-truncation=]
-
-Fix it by allocating a big enough array to print an integer.
-
-Reported-by: kernel test robot <lkp@intel.com>
-Closes: https://lore.kernel.org/oe-kbuild-all/202404191715.LDwMm2gP-lkp@intel.com/
-Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
-Acked-by: Chen-Yu Tsai <wens@csie.org>
-Reviewed-by: Andre Przywara <andre.przywara@arm.com>
-Tested-by: Andre Przywara <andre.przywara@arm.com>
-Reviewed-by: Julian Calaby <julian.calaby@gmail.com>
----
- drivers/cpufreq/sun50i-cpufreq-nvmem.c | 6 ++----
- 1 file changed, 2 insertions(+), 4 deletions(-)
-
---- a/drivers/cpufreq/sun50i-cpufreq-nvmem.c
-+++ b/drivers/cpufreq/sun50i-cpufreq-nvmem.c
-@@ -19,8 +19,6 @@
- #include <linux/pm_opp.h>
- #include <linux/slab.h>
-
--#define MAX_NAME_LEN 7
--
- #define NVMEM_MASK 0x7
- #define NVMEM_SHIFT 5
-
-@@ -208,7 +206,7 @@ static int sun50i_cpufreq_get_efuse(void
- static int sun50i_cpufreq_nvmem_probe(struct platform_device *pdev)
- {
- int *opp_tokens;
-- char name[MAX_NAME_LEN];
-+ char name[] = "speedXXXXXXXXXXX"; /* Integers can take 11 chars max */
- unsigned int cpu, supported_hw;
- struct dev_pm_opp_config config = {};
- int speed;
-@@ -235,7 +233,7 @@ static int sun50i_cpufreq_nvmem_probe(st
- config.supported_hw_count = 1;
- }
-
-- snprintf(name, MAX_NAME_LEN, "speed%d", speed);
-+ snprintf(name, sizeof(name), "speed%d", speed);
- config.prop_name = name;
-
- for_each_possible_cpu(cpu) {
+++ /dev/null
-From 76a6fc5644b2a1c70868bec24a078f784600ef2a Mon Sep 17 00:00:00 2001
-From: Dan Carpenter <dan.carpenter@linaro.org>
-Date: Wed, 24 Apr 2024 14:40:11 +0300
-Subject: [PATCH] cpufreq: sun50i: fix error returns in dt_has_supported_hw()
-
-The dt_has_supported_hw() function returns type bool. That means these
-negative error codes are cast to true but the function should return
-false instead.
-
-Fixes: fa5aec9561cf ("cpufreq: sun50i: Add support for opp_supported_hw")
-Signed-off-by: Dan Carpenter <dan.carpenter@linaro.org>
-Reviewed-by: Andre Przywara <andre.przywara@arm.com>
-Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com>
-Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
----
- drivers/cpufreq/sun50i-cpufreq-nvmem.c | 4 ++--
- 1 file changed, 2 insertions(+), 2 deletions(-)
-
---- a/drivers/cpufreq/sun50i-cpufreq-nvmem.c
-+++ b/drivers/cpufreq/sun50i-cpufreq-nvmem.c
-@@ -136,11 +136,11 @@ static bool dt_has_supported_hw(void)
-
- cpu_dev = get_cpu_device(0);
- if (!cpu_dev)
-- return -ENODEV;
-+ return false;
-
- np = dev_pm_opp_of_get_opp_desc_node(cpu_dev);
- if (!np)
-- return -ENOENT;
-+ return false;
-
- for_each_child_of_node(np, opp) {
- if (of_find_property(opp, "opp-supported-hw", NULL)) {
--- a/arch/arm/boot/dts/allwinner/Makefile
+++ b/arch/arm/boot/dts/allwinner/Makefile
-@@ -219,6 +219,7 @@ dtb-$(CONFIG_MACH_SUN8I) += \
+@@ -220,6 +220,7 @@ dtb-$(CONFIG_MACH_SUN8I) += \
sun8i-a83t-cubietruck-plus.dtb \
sun8i-a83t-tbs-a711.dtb \
sun8i-h2-plus-bananapi-m2-zero.dtb \
projects / thirdparty / openwrt.git / commitdiff
