riscv: dts: spacemit: k1-musepi-pro: enable PCIe ports

Enable the two PCIe controllers along with their associated PHYs. They
are routed to the M.2 M-key connector and to the PCIe slot.

Signed-off-by: Andre Heider <a.heider@gmail.com>
Link: https://patch.msgid.link/20260513071958.29574-6-a.heider@gmail.com
Signed-off-by: Yixun Lan <dlan@kernel.org>

diff --git a/arch/riscv/boot/dts/spacemit/k1-musepi-pro.dts b/arch/riscv/boot/dts/spacemit/k1-musepi-pro.dts
index b284bf416880364e7750c75b662606813df3cccb..898b537ba0bcab9c650615d9d1c281542fa13c3e 100644 (file)
--- a/arch/riscv/boot/dts/spacemit/k1-musepi-pro.dts
+++ b/arch/riscv/boot/dts/spacemit/k1-musepi-pro.dts
@@ -36,6 +36,14 @@
                };
        };
 
+       reg_pcie_vcc_3v3: regulator-pcie-vcc3v3 {
+               compatible = "regulator-fixed";
+               regulator-name = "PCIE_VCC3V3";
+               regulator-min-microvolt = <3300000>;
+               regulator-max-microvolt = <3300000>;
+               regulator-always-on;
+       };
+
        reg_vcc_4v: regulator-vcc-4v {
                compatible = "regulator-fixed";
                regulator-name = "VCC4V0";
@@ -272,6 +280,36 @@
        };
 };
 
+&pcie1_phy {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pcie1_3_cfg>;
+       status = "okay";
+};
+
+&pcie1_port {
+       phys = <&pcie1_phy>;
+       vpcie3v3-supply = <&reg_pcie_vcc_3v3>;
+};
+
+&pcie1 {
+       status = "okay";
+};
+
+&pcie2_phy {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pcie2_4_cfg>;
+       status = "okay";
+};
+
+&pcie2_port {
+       phys = <&pcie2_phy>;
+       vpcie3v3-supply = <&reg_pcie_vcc_3v3>;
+};
+
+&pcie2 {
+       status = "okay";
+};
+
 &qspi {
        pinctrl-names = "default";
        pinctrl-0 = <&qspi_cfg>;