RISC-V: testsuite: Remove redundant vector_hw and zvfh_hw.

This replaces the now-redundant vector_hw and zvfh_hw checks in the
testsuite by riscv_v and riscv_zvfh.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/rvv/autovec/binop/copysign-zvfh-run.c:
	Replace riscv_zvfh_hw with riscv_zvfh.
	* gcc.target/riscv/rvv/autovec/binop/vadd-zvfh-run.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vdiv-zvfh-run.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vmax-zvfh-run.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vmin-zvfh-run.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vmul-zvfh-run.c: Ditto.
	* gcc.target/riscv/rvv/autovec/cond/cond_copysign-zvfh-run.c:
	Ditto.
	* gcc.target/riscv/rvv/autovec/struct/struct_vect_run-10.c:
	Ditto.
	* gcc.target/riscv/rvv/autovec/struct/struct_vect_run-6.c: Allow
	overriding N.
	* gcc.target/riscv/rvv/autovec/unop/abs-zvfh-run.c: Replace
	riscv zvfh_hw with riscv_zvfh.
	* gcc.target/riscv/rvv/autovec/unop/vneg-zvfh-run.c: Ditto.
	* gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-1.c: Ditto.
	* gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-10.c: Ditto.
	* gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-11.c: Ditto.
	* gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-12.c: Ditto.
	* gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-2.c: Ditto.
	* gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-3.c: Ditto.
	* gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-5.c: Ditto.
	* gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-6.c: Ditto.
	* gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-7.c: Ditto.
	* gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-8.c: Ditto.
	* lib/target-supports.exp: Remove riscv_vector_hw and
	riscv_zvfh_hw.

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/copysign-zvfh-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/copysign-zvfh-run.c
index 3bf64ab72ef0d5b538a980d529b28ca397527ffc..e71b6589fc3b524f9f4a6eeb882be0c53ae912ea 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/copysign-zvfh-run.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/copysign-zvfh-run.c
@@ -1,4 +1,4 @@
-/* { dg-do run { target { riscv_v && riscv_zvfh_hw } } } */
+/* { dg-do run { target { riscv_v && riscv_zvfh } } } */
 /* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */
 
 #include "copysign-template.h"

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vadd-zvfh-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vadd-zvfh-run.c
index 2a8618ad09b75db558f96bf10188b9746e3baed0..6c2d096e103bf5d9cc2c574dfb73ca49775a13fa 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vadd-zvfh-run.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vadd-zvfh-run.c
@@ -1,4 +1,4 @@
-/* { dg-do run { target { riscv_v && riscv_zvfh_hw } } } */
+/* { dg-do run { target { riscv_v && riscv_zvfh } } } */
 /* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */
 
 #include "vadd-template.h"

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-zvfh-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-zvfh-run.c
index 1b8e69259cacc2266eafc33dbe0960acdc5773a9..c9f9d83ccb8270693d1add583ae9ddf5dc4dd5ef 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-zvfh-run.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-zvfh-run.c
@@ -1,4 +1,4 @@
-/* { dg-do run { target { riscv_v && riscv_zvfh_hw } } } */
+/* { dg-do run { target { riscv_v && riscv_zvfh } } } */
 /* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */
 
 #include "vdiv-template.h"

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmax-zvfh-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmax-zvfh-run.c
index ea9455ae0593227575d9c45ac8798cffa0235d1c..85e19c1ff43eef19db2fbd7378ccc278aaf1605a 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmax-zvfh-run.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmax-zvfh-run.c
@@ -1,4 +1,4 @@
-/* { dg-do run { target { riscv_v && riscv_zvfh_hw } } } */
+/* { dg-do run { target { riscv_v && riscv_zvfh } } } */
 /* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */
 
 #include "vmax-template.h"

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmin-zvfh-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmin-zvfh-run.c
index 7be92f5c82dd29eeac41edab291990cb46751d95..b24d4f3cb16862e41dff9ccdc2e2d754c027992d 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmin-zvfh-run.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmin-zvfh-run.c
@@ -1,4 +1,4 @@
-/* { dg-do run { target { riscv_v && riscv_zvfh_hw } } } */
+/* { dg-do run { target { riscv_v && riscv_zvfh } } } */
 /* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */
 
 #include "vmin-template.h"

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmul-zvfh-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmul-zvfh-run.c
index 1082695c5dec346f38a116d16febd500d57823e8..63bcf707756a98b6597a47928bea1c614435c344 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmul-zvfh-run.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmul-zvfh-run.c
@@ -1,4 +1,4 @@
-/* { dg-do run { target { riscv_zvfh } } } */
+/* { dg-do run { target { riscv_v && riscv_zvfh } } } */
 /* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */
 
 #include "vmul-template.h"

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_copysign-zvfh-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_copysign-zvfh-run.c
index bdf6eed1c78455cf77f692ca05056df426afdc5f..79a513070347181e488a4532bbd6a7c96f613f1e 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_copysign-zvfh-run.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_copysign-zvfh-run.c
@@ -1,4 +1,4 @@
-/* { dg-do run { target { riscv_v && riscv_zvfh_hw } } } */
+/* { dg-do run { target { riscv_v && riscv_zvfh } } } */
 /* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */
 
 #include "cond_copysign-template.h"

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-10.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-10.c
index 3beca30c361ea117b6a56c47cf8e817093491a05..049280baee57b2b6c3c9ce11fb88e7ff1e19b811 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-10.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-10.c
@@ -1,6 +1,9 @@
-/* { dg-do run { target { riscv_v && riscv_zvfh_hw } } } */
+/* { dg-do run { target { riscv_v && riscv_zvfh } } } */
 /* { dg-additional-options "-std=gnu99 --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */
 
 #define TYPE _Float16
 #define ITYPE int16_t
+
+/* Use a lower iteration count so we do not run into precision problems.  */
+#define N 46
 #include "struct_vect_run-6.c"

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-6.c
index c096888398de9ce06e16fa0b6aecd681b0eb7513..c836bcddb7e005624f2b52b1252a4fe8c5623965 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-6.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-6.c
@@ -3,7 +3,9 @@
 
 #include "struct_vect-6.c"
 
+#ifndef N
 #define N 93
+#endif
 
 TYPE a[N], b[N], c[N], d[N], a2[N], b2[N], c2[N], d2[N], e[N * 8];
 

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/abs-zvfh-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/abs-zvfh-run.c
index 65087d516658f06c53fd6dc82d4c4b4ef6813441..f0c00de9f8fefc86e8d2c40b0f35c81bd77e3476 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/abs-zvfh-run.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/abs-zvfh-run.c
@@ -1,4 +1,4 @@
-/* { dg-do run { target { riscv_zvfh_hw } } } */
+/* { dg-do run { target { riscv_v && riscv_zvfh } } } */
 /* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */
 
 #include "abs-template.h"

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vneg-zvfh-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vneg-zvfh-run.c
index 64c965fea1a6bbb22ff0e25121cdd0ff88abef07..38c8c7ae83d63919e18ec8e7fb775db095f0e2c2 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vneg-zvfh-run.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vneg-zvfh-run.c
@@ -1,4 +1,4 @@
-/* { dg-do run { target { riscv_zvfh_hw } } } */
+/* { dg-do run { target { riscv_v && riscv_zvfh } } } */
 /* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */
 
 #include "vneg-template.h"

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-1.c
index 5661252a0ae9afe6e3a43e5f1c910981fe914d6a..41c573460d90ca8010ccd1681c341d2bcf001a68 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-1.c
@@ -1,4 +1,4 @@
-/* { dg-do run { target { riscv_v && riscv_zvfh_hw } } } */
+/* { dg-do run { target { riscv_v && riscv_zvfh } } } */
 /* { dg-additional-options "--param=riscv-autovec-preference=scalable -ffast-math" } */
 
 #include <assert.h>

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-10.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-10.c
index 1fcd8362ce8cbd4a1c5b096dafeba34129392a05..99ceef0f0cabcd3cbcac0bffbf1b4ae2845bddf7 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-10.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-10.c
@@ -1,4 +1,4 @@
-/* { dg-do run { target { riscv_v && riscv_zvfh_hw } } } */
+/* { dg-do run { target { riscv_v && riscv_zvfh } } } */
 /* { dg-additional-options "--param=riscv-autovec-preference=scalable -ffast-math" } */
 
 #include <assert.h>

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-11.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-11.c
index 8e73095bc124720aa9bacec45e1bccdfc1d1499f..cec71f91210ea11b857ac95f953af76e0cd953c5 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-11.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-11.c
@@ -1,4 +1,4 @@
-/* { dg-do run { target { riscv_v && riscv_zvfh_hw } } } */
+/* { dg-do run { target { riscv_v && riscv_zvfh } } } */
 /* { dg-additional-options "--param=riscv-autovec-preference=scalable -ffast-math" } */
 
 #include <assert.h>

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-12.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-12.c
index 6f04595ae99a9645528b62d0e9c152572e8d01c3..4afdcba522d54abe9e42478ae268215b98e3beb0 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-12.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-12.c
@@ -1,4 +1,4 @@
-/* { dg-do run { target { riscv_v && riscv_zvfh_hw } } } */
+/* { dg-do run { target { riscv_v && riscv_zvfh } } } */
 /* { dg-additional-options "--param=riscv-autovec-preference=scalable -ffast-math" } */
 
 #include <assert.h>

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-2.c
index a3ddeb0b3adcd691891817f6125910106565df1e..ffb8d7f6ec493a2903c560081253efb671fce336 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-2.c
@@ -1,4 +1,4 @@
-/* { dg-do run { target { riscv_v && riscv_zvfh_hw } } } */
+/* { dg-do run { target { riscv_v && riscv_zvfh } } } */
 /* { dg-additional-options "--param=riscv-autovec-preference=scalable -ffast-math" } */
 
 #include <assert.h>

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-3.c
index 47a1803a3287d5b24487b23953c0ff172ae2e5de..5c23112019ee8eb3fd9a2608e1bec092932b13d8 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-3.c
@@ -1,4 +1,4 @@
-/* { dg-do run { target { riscv_v } } } */
+/* { dg-do run { target { riscv_v && riscv_zvfh } } } */
 /* { dg-additional-options "--param=riscv-autovec-preference=scalable -ffast-math" } */
 
 #include <assert.h>

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-5.c
index a5eb47601fd315628b21266fe15e44c8e9721349..a91a51622a35dd1468cf719212be1b474cf91376 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-5.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-5.c
@@ -1,4 +1,4 @@
-/* { dg-do run { target { riscv_v && riscv_zvfh_hw } } } */
+/* { dg-do run { target { riscv_v && riscv_zvfh } } } */
 /* { dg-additional-options "--param=riscv-autovec-preference=scalable -ffast-math" } */
 
 #include <assert.h>

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-6.c
index 046d471ae30cd2d40884639f99b81f567288addb..5b7f000944ecbca7f55c58a5bf3a2b88ab4074f9 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-6.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-6.c
@@ -1,4 +1,4 @@
-/* { dg-do run { target { riscv_v && riscv_zvfh_hw } } } */
+/* { dg-do run { target { riscv_v && riscv_zvfh } } } */
 /* { dg-additional-options "--param=riscv-autovec-preference=scalable -ffast-math" } */
 
 #include <assert.h>

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-7.c
index d10017c690156a1b0c1a6903d3f26ab77d205bc2..f01efa350d7270e63e471a721718a1d4ce48b4fe 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-7.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-7.c
@@ -1,4 +1,4 @@
-/* { dg-do run { target { riscv_v && riscv_zvfh_hw } } } */
+/* { dg-do run { target { riscv_v && riscv_zvfh } } } */
 /* { dg-additional-options "--param=riscv-autovec-preference=scalable -ffast-math" } */
 
 #include <assert.h>

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-8.c
index 2b945f9ef537074076f1c956e80d87fae8c4f689..ed79ac88717aeec8eaa3b044120fe9632c8093bb 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-8.c
@@ -1,4 +1,4 @@
-/* { dg-do run { target { riscv_v && riscv_zvfh_hw } } } */
+/* { dg-do run { target { riscv_v && riscv_zvfh } } } */
 /* { dg-additional-options "--param=riscv-autovec-preference=scalable -ffast-math" } */
 
 #include <assert.h>

diff --git a/gcc/testsuite/lib/target-supports.exp b/gcc/testsuite/lib/target-supports.exp
index 8d874031ffea6306f680e8125fbe7445105e1c72..83eb08ba54ee26f4c9698db4de8bc03447afdd08 100644 (file)
--- a/gcc/testsuite/lib/target-supports.exp
+++ b/gcc/testsuite/lib/target-supports.exp
@@ -1823,55 +1823,6 @@ proc check_linker_plugin_available { } {
   } "-flto -fuse-linker-plugin"]
 }
 
-# Return 1 if the we can build a vector example with proper -march flags
-# and the current target can execute it, 0 otherwise.  Cache the result.
-
-proc check_effective_target_riscv_vector_hw { } {
-
-    return [check_runtime riscv_vector_hw32 {
-        int main (void)
-        {
-            asm ("vsetivli zero,8,e16,m1,ta,ma");
-            asm ("vadd.vv v8,v8,v16" : : : "v8");
-            return 0;
-        }
-    } ""] || [check_runtime riscv_vector_hw64 {
-        int main (void)
-        {
-            asm ("vsetivli zero,8,e16,m1,ta,ma");
-            asm ("vadd.vv v8,v8,v16" : : : "v8");
-            return 0;
-        }
-    } ""]
-}
-
-# Return 1 if the we can build a Zvfh vector example with proper -march flags
-# and the current target can execute it, 0 otherwise.  Cache the result.
-
-proc check_effective_target_riscv_zvfh_hw { } {
-    if ![check_effective_target_riscv_vector_hw] then {
-        return 0
-    }
-
-    return [check_runtime riscv_zvfh_hw32 {
-        int main (void)
-        {
-            asm ("vsetivli zero,8,e16,m1,ta,ma");
-            asm ("vfadd.vv v8,v8,v16" : : : "v8");
-            return 0;
-        }
-    } "-march=rv32gcv_zvfh -mabi=ilp32d"]
-    || [check_runtime riscv_zvfh_hw64 {
-        int main (void)
-        {
-            asm ("vsetivli zero,8,e16,m1,ta,ma");
-            asm ("vfadd.vv v8,v8,v16" : : : "v8");
-            return 0;
-        }
-    } "-march=rv64gcv_zvfh -mabi=lp64d"]
-}
-
-
 # Return 1 if the target is RV32, 0 otherwise.  Cache the result.
 
 proc check_effective_target_rv32 { } {
@@ -11587,7 +11538,7 @@ proc check_vect_support_and_set_flags { } {
     } elseif [istarget amdgcn-*-*] {
         set dg-do-what-default run
     } elseif [istarget riscv64-*-*] {
-       if [check_effective_target_riscv_vector_hw] {
+       if [check_effective_target_riscv_v] {
            lappend DEFAULT_VECTCFLAGS "--param" "riscv-vector-abi"
            set dg-do-what-default run
        } else {