/* The SPARC port says: Nonzero if access to memory by bytes is slow
and undesirable. For RISC chips, it means that access to memory by
bytes is no better than access by words when possible, so grab a
- whole word and maybe make use of that. */
-#define SLOW_BYTE_ACCESS 1
+ whole word and maybe make use of that.
+ BPF programs will be JIT-ed to various architectures, so we cannot
+ say for certain what the access patterns on the final architecture
+ are. From the BPF verifier perspective, smaller loads are actually
+ preferable so set this to zero. */
+#define SLOW_BYTE_ACCESS 0
/* Threshold of number of scalar memory-to-memory move instructions,
_below_ which a sequence of insns should be generated instead of a
--- /dev/null
+/* PR target/123556.
+ Test that we do not load the bit-fields with a larger aligned load
+ that crosses struct boundaries, which the BPF verifier rejects. */
+/* { dg-do compile } */
+/* { dg-options "-O2 -S -dA -masm=normal" } */
+
+struct problem
+{
+ unsigned char f1;
+ unsigned char f2;
+ struct {
+ unsigned short id;
+ unsigned short val;
+ } stmemb[2];
+
+ unsigned char ba:2;
+ unsigned char bb:3;
+
+ unsigned short f3;
+};
+
+int foo (struct problem *p)
+{
+ if (p->bb != 1)
+ return -1;
+ if (p->ba >= 2)
+ return -1;
+
+ return 0;
+}
+
+/* { dg-final { scan-assembler-not "ldxw" } } */
+/* { dg-final { scan-assembler-not "ldxdw" } } */