arm64: dts: rockchip: Add the vdpu383 Video Decoder on rk3576

Add the vdpu383 Video Decoder variant to the RK3576 device tree.

Also allow using the dedicated SRAM as a pool.

Signed-off-by: Detlev Casanova <detlev.casanova@collabora.com>
Link: https://patch.msgid.link/20251020212009.8852-3-detlev.casanova@collabora.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>

diff --git a/arch/arm64/boot/dts/rockchip/rk3576.dtsi b/arch/arm64/boot/dts/rockchip/rk3576.dtsi
index 792857aee4f7a3d07b33555b8ba00e09b54f4065..7286d968e2b0626e001a6a746cba850dacd30b7c 100644 (file)
--- a/arch/arm64/boot/dts/rockchip/rk3576.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3576.dtsi
@@ -1279,6 +1279,41 @@
                        status = "disabled";
                };
 
+               vdec: video-codec@27b00000 {
+                       compatible = "rockchip,rk3576-vdec";
+                       reg = <0x0 0x27b00100 0x0 0x500>,
+                             <0x0 0x27b00000 0x0 0x100>,
+                             <0x0 0x27b00600 0x0 0x100>;
+                       reg-names = "function", "link", "cache";
+                       interrupts = <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&cru ACLK_RKVDEC_ROOT>, <&cru HCLK_RKVDEC>,
+                                <&cru ACLK_RKVDEC_ROOT_BAK>, <&cru CLK_RKVDEC_CORE>,
+                                <&cru CLK_RKVDEC_HEVC_CA>;
+                       clock-names = "axi", "ahb", "cabac", "core", "hevc_cabac";
+                       assigned-clocks = <&cru ACLK_RKVDEC_ROOT>, <&cru CLK_RKVDEC_CORE>,
+                                         <&cru ACLK_RKVDEC_ROOT_BAK>, <&cru CLK_RKVDEC_HEVC_CA>;
+                       assigned-clock-rates = <600000000>, <600000000>,
+                                              <500000000>, <1000000000>;
+                       iommus = <&vdec_mmu>;
+                       power-domains = <&power RK3576_PD_VDEC>;
+                       resets = <&cru SRST_A_RKVDEC_BIU>, <&cru SRST_H_RKVDEC_BIU>,
+                                <&cru SRST_H_RKVDEC>, <&cru SRST_RKVDEC_CORE>,
+                                <&cru SRST_RKVDEC_HEVC_CA>;
+                       reset-names = "axi", "ahb", "cabac", "core", "hevc_cabac";
+                       sram = <&rkvdec_sram>;
+               };
+
+               vdec_mmu: iommu@27b00800 {
+                       compatible = "rockchip,rk3576-iommu", "rockchip,rk3568-iommu";
+                       reg = <0x0 0x27b00800 0x0 0x40>, <0x0 0x27b00900 0x0 0x40>;
+                       interrupts = <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&cru CLK_RKVDEC_CORE>, <&cru HCLK_RKVDEC>;
+                       clock-names = "aclk", "iface";
+                       power-domains = <&power RK3576_PD_VDEC>;
+                       rockchip,disable-mmu-reset;
+                       #iommu-cells = <0>;
+               };
+
                vop: vop@27d00000 {
                        compatible = "rockchip,rk3576-vop";
                        reg = <0x0 0x27d00000 0x0 0x3000>, <0x0 0x27d05000 0x0 0x1000>;
@@ -2684,6 +2719,7 @@
                        /* start address and size should be 4k align */
                        rkvdec_sram: rkvdec-sram@0 {
                                reg = <0x0 0x78000>;
+                               pool;
                        };
                };