KVM: arm64: gic: Enable GICv3 CPUIF trapping on GICv5 hosts if required

Factor out the enable (and printing of) the GICv3 CPUIF traps from the
main GICv3 probe into a separate function. Call said function from the
GICv5 probe for legacy support, ensuring that any required GICv3 CPUIF
traps on GICv5 hosts will be correctly handled, rather than injecting
an undef into the guest.

Signed-off-by: Sascha Bischoff <sascha.bischoff@arm.com>
Link: https://patch.msgid.link/20251208152724.3637157-3-sascha.bischoff@arm.com
Signed-off-by: Marc Zyngier <maz@kernel.org>

diff --git a/arch/arm64/kvm/vgic/vgic-v3.c b/arch/arm64/kvm/vgic/vgic-v3.c
index 1d6dd1b545bdd6cebf5f738c9aa8e29bdcea58a5..4b03a726f164556cdd5151b996174dfde5c5caa4 100644 (file)
--- a/arch/arm64/kvm/vgic/vgic-v3.c
+++ b/arch/arm64/kvm/vgic/vgic-v3.c
@@ -880,6 +880,20 @@ void noinstr kvm_compute_ich_hcr_trap_bits(struct alt_instr *alt,
        *updptr = cpu_to_le32(insn);
 }
 
+void vgic_v3_enable_cpuif_traps(void)
+{
+       u64 traps = vgic_ich_hcr_trap_bits();
+
+       if (traps) {
+               kvm_info("GICv3 sysreg trapping enabled ([%s%s%s%s], reduced performance)\n",
+                        (traps & ICH_HCR_EL2_TALL0) ? "G0" : "",
+                        (traps & ICH_HCR_EL2_TALL1) ? "G1" : "",
+                        (traps & ICH_HCR_EL2_TC)    ? "C"  : "",
+                        (traps & ICH_HCR_EL2_TDIR)  ? "D"  : "");
+               static_branch_enable(&vgic_v3_cpuif_trap);
+       }
+}
+
 /**
  * vgic_v3_probe - probe for a VGICv3 compatible interrupt controller
  * @info:      pointer to the GIC description
@@ -891,7 +905,6 @@ int vgic_v3_probe(const struct gic_kvm_info *info)
 {
        u64 ich_vtr_el2 = kvm_call_hyp_ret(__vgic_v3_get_gic_config);
        bool has_v2;
-       u64 traps;
        int ret;
 
        has_v2 = ich_vtr_el2 >> 63;
@@ -955,15 +968,7 @@ int vgic_v3_probe(const struct gic_kvm_info *info)
                kvm_vgic_global_state.ich_vtr_el2 &= ~ICH_VTR_EL2_SEIS;
        }
 
-       traps = vgic_ich_hcr_trap_bits();
-       if (traps) {
-               kvm_info("GICv3 sysreg trapping enabled ([%s%s%s%s], reduced performance)\n",
-                        (traps & ICH_HCR_EL2_TALL0) ? "G0" : "",
-                        (traps & ICH_HCR_EL2_TALL1) ? "G1" : "",
-                        (traps & ICH_HCR_EL2_TC)    ? "C"  : "",
-                        (traps & ICH_HCR_EL2_TDIR)  ? "D"  : "");
-               static_branch_enable(&vgic_v3_cpuif_trap);
-       }
+       vgic_v3_enable_cpuif_traps();
 
        kvm_vgic_global_state.vctrl_base = NULL;
        kvm_vgic_global_state.type = VGIC_V3;

diff --git a/arch/arm64/kvm/vgic/vgic-v5.c b/arch/arm64/kvm/vgic/vgic-v5.c
index 2d3811f4e1174907a01cf72f0ca58076baf166d0..331651087e2c7db984ea1755eef698654fefbfe7 100644 (file)
--- a/arch/arm64/kvm/vgic/vgic-v5.c
+++ b/arch/arm64/kvm/vgic/vgic-v5.c
@@ -48,5 +48,7 @@ int vgic_v5_probe(const struct gic_kvm_info *info)
        static_branch_enable(&kvm_vgic_global_state.gicv3_cpuif);
        kvm_info("GCIE legacy system register CPU interface\n");
 
+       vgic_v3_enable_cpuif_traps();
+
        return 0;
 }

diff --git a/arch/arm64/kvm/vgic/vgic.h b/arch/arm64/kvm/vgic/vgic.h
index 5f0fc96b4dc2908030554853a5fa086683547a70..c9b3bb07e483c115ba987ab63e91ee4b12599fb6 100644 (file)
--- a/arch/arm64/kvm/vgic/vgic.h
+++ b/arch/arm64/kvm/vgic/vgic.h
@@ -324,6 +324,7 @@ void vgic_v3_configure_hcr(struct kvm_vcpu *vcpu, struct ap_list_summary *als);
 void vgic_v3_set_vmcr(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcr);
 void vgic_v3_get_vmcr(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcr);
 void vgic_v3_reset(struct kvm_vcpu *vcpu);
+void vgic_v3_enable_cpuif_traps(void);
 int vgic_v3_probe(const struct gic_kvm_info *info);
 int vgic_v3_map_resources(struct kvm *kvm);
 int vgic_v3_lpi_sync_pending_status(struct kvm *kvm, struct vgic_irq *irq);