* non-coherent and require a CPU:WC mapping.
*/
if ((!bo->cpu_caching && bo->flags & XE_BO_FLAG_SCANOUT) ||
- (xe->info.graphics_verx100 >= 1270 &&
- bo->flags & XE_BO_FLAG_PAGETABLE))
+ (!xe->info.has_cached_pt && bo->flags & XE_BO_FLAG_PAGETABLE))
caching = ttm_write_combined;
}
u8 has_asid:1;
/** @info.has_atomic_enable_pte_bit: Device has atomic enable PTE bit */
u8 has_atomic_enable_pte_bit:1;
+ /** @info.has_cached_pt: Supports caching pagetable */
+ u8 has_cached_pt:1;
/** @info.has_device_atomics_on_smem: Supports device atomics on SMEM */
u8 has_device_atomics_on_smem:1;
/** @info.has_fan_control: Device supports fan control */
.pre_gmdid_media_ip = &media_ip_xem,
PLATFORM(TIGERLAKE),
.dma_mask_size = 39,
+ .has_cached_pt = true,
.has_display = true,
.has_llc = true,
.has_sriov = true,
.pre_gmdid_media_ip = &media_ip_xem,
PLATFORM(ROCKETLAKE),
.dma_mask_size = 39,
+ .has_cached_pt = true,
.has_display = true,
.has_llc = true,
.max_gt_per_tile = 1,
.pre_gmdid_media_ip = &media_ip_xem,
PLATFORM(ALDERLAKE_S),
.dma_mask_size = 39,
+ .has_cached_pt = true,
.has_display = true,
.has_llc = true,
.has_sriov = true,
.pre_gmdid_media_ip = &media_ip_xem,
PLATFORM(ALDERLAKE_P),
.dma_mask_size = 39,
+ .has_cached_pt = true,
.has_display = true,
.has_llc = true,
.has_sriov = true,
.pre_gmdid_media_ip = &media_ip_xem,
PLATFORM(ALDERLAKE_N),
.dma_mask_size = 39,
+ .has_cached_pt = true,
.has_display = true,
.has_llc = true,
.has_sriov = true,
xe->info.vram_flags = desc->vram_flags;
xe->info.is_dgfx = desc->is_dgfx;
+ xe->info.has_cached_pt = desc->has_cached_pt;
xe->info.has_fan_control = desc->has_fan_control;
/* runtime fusing may force flat_ccs to disabled later */
xe->info.has_flat_ccs = desc->has_flat_ccs;