arm64: dts: imx8ulp: Add CSI and ISI Nodes

The CSI-2 in the i.MX8ULP is almost identical to the version present
in the i.MX8QXP/QM and is routed to the ISI. Add both the ISI and CSI
nodes and mark them as disabled by default since capture is dependent
on an attached camera.

Reviewed-by: Frank Li <Frank.Li@nxp.com>
Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Guoniu Zhou <guoniu.zhou@nxp.com>
Signed-off-by: Frank Li <Frank.Li@nxp.com>

diff --git a/arch/arm64/boot/dts/freescale/imx8ulp.dtsi b/arch/arm64/boot/dts/freescale/imx8ulp.dtsi
index 1de3ad60c6aa7791ba6833df32fc57e650d3f610..17caf3703fb17a1a264d9bf98bf4a55735666570 100644 (file)
--- a/arch/arm64/boot/dts/freescale/imx8ulp.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8ulp.dtsi
@@ -858,6 +858,72 @@
                                dma-names = "rx", "tx";
                                status = "disabled";
                        };
+
+                       isi: isi@2dac0000 {
+                               compatible = "fsl,imx8ulp-isi";
+                               reg = <0x2dac0000 0x10000>;
+                               interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
+                               clocks = <&pcc5 IMX8ULP_CLK_ISI>,
+                                        <&cgc2 IMX8ULP_CLK_LPAV_AXI_DIV>;
+                               clock-names = "axi", "apb";
+                               power-domains = <&scmi_devpd IMX8ULP_PD_ISI>;
+                               status = "disabled";
+
+                               ports {
+                                       #address-cells = <1>;
+                                       #size-cells = <0>;
+
+                                       port@0 {
+                                               reg = <0>;
+                                               isi_in: endpoint {
+                                                       remote-endpoint = <&mipi_csi_out>;
+                                               };
+                                       };
+                               };
+                       };
+
+                       mipi_csi: csi@2daf0000 {
+                               compatible = "fsl,imx8ulp-mipi-csi2";
+                               reg = <0x2daf0000 0x10000>,
+                                     <0x2dad0000 0x10000>;
+                               clocks = <&pcc5 IMX8ULP_CLK_CSI>,
+                                        <&pcc5 IMX8ULP_CLK_CSI_CLK_ESC>,
+                                        <&pcc5 IMX8ULP_CLK_CSI_CLK_UI>,
+                                        <&pcc5 IMX8ULP_CLK_CSI_REGS>;
+                               clock-names = "core", "esc", "ui", "pclk";
+                               assigned-clocks = <&pcc5 IMX8ULP_CLK_CSI>,
+                                                 <&pcc5 IMX8ULP_CLK_CSI_CLK_ESC>,
+                                                 <&pcc5 IMX8ULP_CLK_CSI_CLK_UI>,
+                                                 <&pcc5 IMX8ULP_CLK_CSI_REGS>;
+                               assigned-clock-parents = <&cgc2 IMX8ULP_CLK_PLL4_PFD1_DIV1>,
+                                                        <&cgc2 IMX8ULP_CLK_PLL4_PFD1_DIV2>,
+                                                        <&cgc2 IMX8ULP_CLK_PLL4_PFD0_DIV1>;
+                               assigned-clock-rates = <200000000>,
+                                                      <80000000>,
+                                                      <100000000>,
+                                                      <79200000>;
+                               power-domains = <&scmi_devpd IMX8ULP_PD_MIPI_CSI>;
+                               resets = <&pcc5 5>,     /* PCC5_CSI_REGS_SWRST */
+                                        <&pcc5 6>;     /* PCC5_CSI_SWRST> */
+                               status = "disabled";
+
+                               ports {
+                                       #address-cells = <1>;
+                                       #size-cells = <0>;
+
+                                       port@0 {
+                                               reg = <0>;
+                                       };
+
+                                       port@1 {
+                                               reg = <1>;
+
+                                               mipi_csi_out: endpoint {
+                                                       remote-endpoint = <&isi_in>;
+                                               };
+                                       };
+                               };
+                       };
                };
 
                gpiod: gpio@2e200000 {