/* DW-HDMI Controller >= 0x200a are at least compliant with SCDC version 1 */
#define SCDC_MIN_SOURCE_VERSION 0x1
-#define HDMI14_MAX_TMDSCLK 340000000
-
static const u16 csc_coeff_default[3][4] = {
{ 0x2000, 0x0000, 0x0000, 0x0000 },
{ 0x0000, 0x2000, 0x0000, 0x0000 },
/* Control for TMDS Bit Period/TMDS Clock-Period Ratio */
if (dw_hdmi_support_scdc(hdmi, display)) {
- if (mtmdsclock > HDMI14_MAX_TMDSCLK)
+ if (mtmdsclock > HDMI_1_3_TMDS_CHAR_RATE_MAX_HZ)
drm_scdc_set_high_tmds_clock_ratio(hdmi->curr_conn, 1);
else
drm_scdc_set_high_tmds_clock_ratio(hdmi->curr_conn, 0);
}
/* Wait for resuming transmission of TMDS clock and data */
- if (mtmdsclock > HDMI14_MAX_TMDSCLK)
+ if (mtmdsclock > HDMI_1_3_TMDS_CHAR_RATE_MAX_HZ)
msleep(100);
return dw_hdmi_phy_power_on(hdmi);
/* Set up HDMI_FC_INVIDCONF */
inv_val = (hdmi->hdmi_data.hdcp_enable ||
(dw_hdmi_support_scdc(hdmi, display) &&
- (vmode->mtmdsclock > HDMI14_MAX_TMDSCLK ||
+ (vmode->mtmdsclock > HDMI_1_3_TMDS_CHAR_RATE_MAX_HZ ||
hdmi_info->scdc.scrambling.low_rates)) ?
HDMI_FC_INVIDCONF_HDCP_KEEPOUT_ACTIVE :
HDMI_FC_INVIDCONF_HDCP_KEEPOUT_INACTIVE);
/* Scrambling Control */
if (dw_hdmi_support_scdc(hdmi, display)) {
- if (vmode->mtmdsclock > HDMI14_MAX_TMDSCLK ||
+ if (vmode->mtmdsclock > HDMI_1_3_TMDS_CHAR_RATE_MAX_HZ ||
hdmi_info->scdc.scrambling.low_rates) {
/*
* HDMI2.0 Specifies the following procedure: