parisc: fix a possible DMA corruption

commit 7ae04ba36b381bffe2471eff3a93edced843240f upstream.

ARCH_DMA_MINALIGN was defined as 16 - this is too small - it may be
possible that two unrelated 16-byte allocations share a cache line. If
one of these allocations is written using DMA and the other is written
using cached write, the value that was written with DMA may be
corrupted.

This commit changes ARCH_DMA_MINALIGN to be 128 on PA20 and 32 on PA1.1 -
that's the largest possible cache line size.

As different parisc microarchitectures have different cache line size, we
define arch_slab_minalign(), cache_line_size() and
dma_get_cache_alignment() so that the kernel may tune slab cache
parameters dynamically, based on the detected cache line size.

Signed-off-by: Mikulas Patocka <mpatocka@redhat.com>
Cc: stable@vger.kernel.org
Signed-off-by: Helge Deller <deller@gmx.de>
Signed-off-by: Mingli Yu <mingli.yu@windriver.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

diff --git a/arch/parisc/Kconfig b/arch/parisc/Kconfig
index 6ac0c4b98e281303a07dd9685c214f6cca3b5fe7..9888e0b3f67518a001fdb350327582d65637dac9 100644 (file)
--- a/arch/parisc/Kconfig
+++ b/arch/parisc/Kconfig
@@ -15,6 +15,7 @@ config PARISC
        select ARCH_SPLIT_ARG64 if !64BIT
        select ARCH_SUPPORTS_HUGETLBFS if PA20
        select ARCH_SUPPORTS_MEMORY_FAILURE
+       select ARCH_HAS_CACHE_LINE_SIZE
        select DMA_OPS
        select RTC_CLASS
        select RTC_DRV_GENERIC

diff --git a/arch/parisc/include/asm/cache.h b/arch/parisc/include/asm/cache.h
index d53e9e27dba007b5d4e44a1a3759a23c1bf74cb2..99e26c686f7ffb2efcf3c759765f929671f8bee8 100644 (file)
--- a/arch/parisc/include/asm/cache.h
+++ b/arch/parisc/include/asm/cache.h
@@ -20,7 +20,16 @@
 
 #define SMP_CACHE_BYTES L1_CACHE_BYTES
 
-#define ARCH_DMA_MINALIGN      L1_CACHE_BYTES
+#ifdef CONFIG_PA20
+#define ARCH_DMA_MINALIGN      128
+#else
+#define ARCH_DMA_MINALIGN      32
+#endif
+#define ARCH_KMALLOC_MINALIGN  16      /* ldcw requires 16-byte alignment */
+
+#define arch_slab_minalign()   ((unsigned)dcache_stride)
+#define cache_line_size()      dcache_stride
+#define dma_get_cache_alignment cache_line_size
 
 #define __read_mostly __section(".data..read_mostly")