RISC-V: Add test for vec_duplicate + vrem.vv combine case 0 with GR2VR cost 0, 2...

Add asm dump check test for vec_duplicate + vrem.vv combine to vrem.vx,
with the GR2VR cost is 0, 2 and 15.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i16.c: Add asm check
	for vrem.vx combine.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i32.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i64.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i8.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i16.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i32.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i64.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i8.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i16.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i32.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i64.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i8.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx_binary_data.h: Add test
	data for run test.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx_vrem-run-1-i16.c: New test.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx_vrem-run-1-i32.c: New test.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx_vrem-run-1-i64.c: New test.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx_vrem-run-1-i8.c: New test.

Signed-off-by: Pan Li <pan2.li@intel.com>

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i16.c
index d88e76b5d99cae796a0c107a7e2718eaa419833c..893d910538caa94ae118bb823010addcb48289e2 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i16.c
@@ -13,6 +13,7 @@ DEF_VX_BINARY_CASE_0_WRAP(T, |, or)
 DEF_VX_BINARY_CASE_0_WRAP(T, ^, xor)
 DEF_VX_BINARY_CASE_0_WRAP(T, *, mul)
 DEF_VX_BINARY_CASE_0_WRAP(T, /, div)
+DEF_VX_BINARY_CASE_0_WRAP(T, %, rem)
 
 /* { dg-final { scan-assembler-times {vadd.vx} 1 } } */
 /* { dg-final { scan-assembler-times {vsub.vx} 1 } } */
@@ -22,3 +23,4 @@ DEF_VX_BINARY_CASE_0_WRAP(T, /, div)
 /* { dg-final { scan-assembler-times {vxor.vx} 1 } } */
 /* { dg-final { scan-assembler-times {vmul.vx} 1 } } */
 /* { dg-final { scan-assembler-times {vdiv.vx} 1 } } */
+/* { dg-final { scan-assembler-times {vrem.vx} 1 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i32.c
index 53189c21d0413446a76a578e093d5ff514a6e414..26170de40d0cbbe62aaed79308749a94140835ec 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i32.c
@@ -13,6 +13,7 @@ DEF_VX_BINARY_CASE_0_WRAP(T, |, or)
 DEF_VX_BINARY_CASE_0_WRAP(T, ^, xor)
 DEF_VX_BINARY_CASE_0_WRAP(T, *, mul)
 DEF_VX_BINARY_CASE_0_WRAP(T, /, div)
+DEF_VX_BINARY_CASE_0_WRAP(T, %, rem)
 
 /* { dg-final { scan-assembler-times {vadd.vx} 1 } } */
 /* { dg-final { scan-assembler-times {vsub.vx} 1 } } */
@@ -22,3 +23,4 @@ DEF_VX_BINARY_CASE_0_WRAP(T, /, div)
 /* { dg-final { scan-assembler-times {vxor.vx} 1 } } */
 /* { dg-final { scan-assembler-times {vmul.vx} 1 } } */
 /* { dg-final { scan-assembler-times {vdiv.vx} 1 } } */
+/* { dg-final { scan-assembler-times {vrem.vx} 1 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i64.c
index 5059beb4c6de80ec4deb169f47f5ba28aaf0c518..04d1fcb5f81fc0da77f300987240060c6f1adb85 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i64.c
@@ -13,6 +13,7 @@ DEF_VX_BINARY_CASE_0_WRAP(T, |, or)
 DEF_VX_BINARY_CASE_0_WRAP(T, ^, xor)
 DEF_VX_BINARY_CASE_0_WRAP(T, *, mul)
 DEF_VX_BINARY_CASE_0_WRAP(T, /, div)
+DEF_VX_BINARY_CASE_0_WRAP(T, %, rem)
 
 /* { dg-final { scan-assembler-times {vadd.vx} 1 } } */
 /* { dg-final { scan-assembler-times {vsub.vx} 1 } } */
@@ -22,3 +23,4 @@ DEF_VX_BINARY_CASE_0_WRAP(T, /, div)
 /* { dg-final { scan-assembler-times {vxor.vx} 1 } } */
 /* { dg-final { scan-assembler-times {vmul.vx} 1 } } */
 /* { dg-final { scan-assembler-times {vdiv.vx} 1 } } */
+/* { dg-final { scan-assembler-times {vrem.vx} 1 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i8.c
index 4bbe5a40ee0e3c291434fd714e96e3c13827c308..89d37af3114ee66a9680750e0d777d5baa3ab6dd 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i8.c
@@ -13,6 +13,7 @@ DEF_VX_BINARY_CASE_0_WRAP(T, |, or)
 DEF_VX_BINARY_CASE_0_WRAP(T, ^, xor)
 DEF_VX_BINARY_CASE_0_WRAP(T, *, mul)
 DEF_VX_BINARY_CASE_0_WRAP(T, /, div)
+DEF_VX_BINARY_CASE_0_WRAP(T, %, rem)
 
 /* { dg-final { scan-assembler-times {vadd.vx} 1 } } */
 /* { dg-final { scan-assembler-times {vsub.vx} 1 } } */
@@ -22,3 +23,4 @@ DEF_VX_BINARY_CASE_0_WRAP(T, /, div)
 /* { dg-final { scan-assembler-times {vxor.vx} 1 } } */
 /* { dg-final { scan-assembler-times {vmul.vx} 1 } } */
 /* { dg-final { scan-assembler-times {vdiv.vx} 1 } } */
+/* { dg-final { scan-assembler-times {vrem.vx} 1 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i16.c
index 0437db48f59f076267ca02774e6cdcb0b806b9f6..b9f8bd9365a62d916e98d598d4df34b5dcf5a220 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i16.c
@@ -13,6 +13,7 @@ DEF_VX_BINARY_CASE_0_WRAP(T, |, or)
 DEF_VX_BINARY_CASE_0_WRAP(T, ^, xor)
 DEF_VX_BINARY_CASE_0_WRAP(T, *, mul)
 DEF_VX_BINARY_CASE_0_WRAP(T, /, div)
+DEF_VX_BINARY_CASE_0_WRAP(T, %, rem)
 
 /* { dg-final { scan-assembler-not {vadd.vx} } } */
 /* { dg-final { scan-assembler-not {vsub.vx} } } */
@@ -22,3 +23,4 @@ DEF_VX_BINARY_CASE_0_WRAP(T, /, div)
 /* { dg-final { scan-assembler-not {vxor.vx} } } */
 /* { dg-final { scan-assembler-not {vmul.vx} } } */
 /* { dg-final { scan-assembler-not {vdiv.vx} } } */
+/* { dg-final { scan-assembler-not {vrem.vx} } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i32.c
index 95ed403e1eefcb6d218e40e6850215bb80548f94..d2be881904ee4a45b8dde4bd4bcbb27b47bbf9f5 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i32.c
@@ -13,6 +13,7 @@ DEF_VX_BINARY_CASE_0_WRAP(T, |, or)
 DEF_VX_BINARY_CASE_0_WRAP(T, ^, xor)
 DEF_VX_BINARY_CASE_0_WRAP(T, *, mul)
 DEF_VX_BINARY_CASE_0_WRAP(T, /, div)
+DEF_VX_BINARY_CASE_0_WRAP(T, %, rem)
 
 /* { dg-final { scan-assembler-not {vadd.vx} } } */
 /* { dg-final { scan-assembler-not {vsub.vx} } } */
@@ -22,3 +23,4 @@ DEF_VX_BINARY_CASE_0_WRAP(T, /, div)
 /* { dg-final { scan-assembler-not {vxor.vx} } } */
 /* { dg-final { scan-assembler-not {vmul.vx} } } */
 /* { dg-final { scan-assembler-not {vdiv.vx} } } */
+/* { dg-final { scan-assembler-not {vrem.vx} } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i64.c
index f8912a0bac6cb2d97941e195aefb64fb400e3ff3..d1b85ee04fb957701e824ec4885cd1e5c10e7183 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i64.c
@@ -13,6 +13,7 @@ DEF_VX_BINARY_CASE_0_WRAP(T, |, or)
 DEF_VX_BINARY_CASE_0_WRAP(T, ^, xor)
 DEF_VX_BINARY_CASE_0_WRAP(T, *, mul)
 DEF_VX_BINARY_CASE_0_WRAP(T, /, div)
+DEF_VX_BINARY_CASE_0_WRAP(T, %, rem)
 
 /* { dg-final { scan-assembler-not {vadd.vx} } } */
 /* { dg-final { scan-assembler-not {vsub.vx} } } */
@@ -22,3 +23,4 @@ DEF_VX_BINARY_CASE_0_WRAP(T, /, div)
 /* { dg-final { scan-assembler-not {vxor.vx} } } */
 /* { dg-final { scan-assembler-not {vmul.vx} } } */
 /* { dg-final { scan-assembler-not {vdiv.vx} } } */
+/* { dg-final { scan-assembler-not {vrem.vx} } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i8.c
index 3c8f9154a2479f915436793c21c2d1f079b03657..30a39282081cf197cce125746c7a68c885e5556a 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i8.c
@@ -13,6 +13,7 @@ DEF_VX_BINARY_CASE_0_WRAP(T, |, or)
 DEF_VX_BINARY_CASE_0_WRAP(T, ^, xor)
 DEF_VX_BINARY_CASE_0_WRAP(T, *, mul)
 DEF_VX_BINARY_CASE_0_WRAP(T, /, div)
+DEF_VX_BINARY_CASE_0_WRAP(T, %, rem)
 
 /* { dg-final { scan-assembler-not {vadd.vx} } } */
 /* { dg-final { scan-assembler-not {vsub.vx} } } */
@@ -22,3 +23,4 @@ DEF_VX_BINARY_CASE_0_WRAP(T, /, div)
 /* { dg-final { scan-assembler-not {vxor.vx} } } */
 /* { dg-final { scan-assembler-not {vmul.vx} } } */
 /* { dg-final { scan-assembler-not {vdiv.vx} } } */
+/* { dg-final { scan-assembler-not {vrem.vx} } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i16.c
index f49dae498bf266f62bfc7499827f0f6a6275dc06..5210c0da3632f532f0146b68c723fe7730d0bfb7 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i16.c
@@ -13,6 +13,7 @@ DEF_VX_BINARY_CASE_0_WRAP(T, |, or)
 DEF_VX_BINARY_CASE_0_WRAP(T, ^, xor)
 DEF_VX_BINARY_CASE_0_WRAP(T, *, mul)
 DEF_VX_BINARY_CASE_0_WRAP(T, /, div)
+DEF_VX_BINARY_CASE_0_WRAP(T, %, rem)
 
 /* { dg-final { scan-assembler-not {vadd.vx} } } */
 /* { dg-final { scan-assembler-not {vsub.vx} } } */
@@ -22,3 +23,4 @@ DEF_VX_BINARY_CASE_0_WRAP(T, /, div)
 /* { dg-final { scan-assembler-not {vxor.vx} } } */
 /* { dg-final { scan-assembler-not {vmul.vx} } } */
 /* { dg-final { scan-assembler-not {vdiv.vx} } } */
+/* { dg-final { scan-assembler-not {vrem.vx} } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i32.c
index 8f502a31c6cc89c3d914443cce30462463d41ed3..5b0db088e62f2be44dc8a655363657f5163eb50d 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i32.c
@@ -13,6 +13,7 @@ DEF_VX_BINARY_CASE_0_WRAP(T, |, or)
 DEF_VX_BINARY_CASE_0_WRAP(T, ^, xor)
 DEF_VX_BINARY_CASE_0_WRAP(T, *, mul)
 DEF_VX_BINARY_CASE_0_WRAP(T, /, div)
+DEF_VX_BINARY_CASE_0_WRAP(T, %, rem)
 
 /* { dg-final { scan-assembler-not {vadd.vx} } } */
 /* { dg-final { scan-assembler-not {vsub.vx} } } */
@@ -22,3 +23,4 @@ DEF_VX_BINARY_CASE_0_WRAP(T, /, div)
 /* { dg-final { scan-assembler-not {vxor.vx} } } */
 /* { dg-final { scan-assembler-not {vmul.vx} } } */
 /* { dg-final { scan-assembler-not {vdiv.vx} } } */
+/* { dg-final { scan-assembler-not {vrem.vx} } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i64.c
index 3277bf24453a7e1c4a6b2f77517ae0239ea93d8a..8d528d8b7c90ca5cb271ae71e7c3d63815fd6aa1 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i64.c
@@ -13,6 +13,7 @@ DEF_VX_BINARY_CASE_0_WRAP(T, |, or)
 DEF_VX_BINARY_CASE_0_WRAP(T, ^, xor)
 DEF_VX_BINARY_CASE_0_WRAP(T, *, mul)
 DEF_VX_BINARY_CASE_0_WRAP(T, /, div)
+DEF_VX_BINARY_CASE_0_WRAP(T, %, rem)
 
 /* { dg-final { scan-assembler-not {vadd.vx} } } */
 /* { dg-final { scan-assembler-not {vsub.vx} } } */
@@ -22,3 +23,4 @@ DEF_VX_BINARY_CASE_0_WRAP(T, /, div)
 /* { dg-final { scan-assembler-not {vxor.vx} } } */
 /* { dg-final { scan-assembler-not {vmul.vx} } } */
 /* { dg-final { scan-assembler-not {vdiv.vx} } } */
+/* { dg-final { scan-assembler-not {vrem.vx} } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i8.c
index 25ed2ad18ce86deb0ddf78fcf9c236af829d0686..85e79ac1d6b171f9d29a7e59061038d1e8d805a8 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i8.c
@@ -13,6 +13,7 @@ DEF_VX_BINARY_CASE_0_WRAP(T, |, or)
 DEF_VX_BINARY_CASE_0_WRAP(T, ^, xor)
 DEF_VX_BINARY_CASE_0_WRAP(T, *, mul)
 DEF_VX_BINARY_CASE_0_WRAP(T, /, div)
+DEF_VX_BINARY_CASE_0_WRAP(T, %, rem)
 
 /* { dg-final { scan-assembler-not {vadd.vx} } } */
 /* { dg-final { scan-assembler-not {vsub.vx} } } */
@@ -22,3 +23,4 @@ DEF_VX_BINARY_CASE_0_WRAP(T, /, div)
 /* { dg-final { scan-assembler-not {vxor.vx} } } */
 /* { dg-final { scan-assembler-not {vmul.vx} } } */
 /* { dg-final { scan-assembler-not {vdiv.vx} } } */
+/* { dg-final { scan-assembler-not {vrem.vx} } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_binary_data.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_binary_data.h
index 5130709050ddb4a595050768bc13dac25c993ee0..82391fc25680f1c3aa6ba44dd4d028ab1204a526 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_binary_data.h
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_binary_data.h
@@ -2946,4 +2946,200 @@ uint64_t TEST_BINARY_DATA(uint64_t, div)[][3][N] =
   },
 };
 
+int8_t TEST_BINARY_DATA(int8_t, rem)[][3][N] =
+{
+  {
+    { 2 },
+    {
+       2,  2,  2,  2,
+       1,  1,  1,  1,
+      -1, -1, -1, -1,
+      -2, -2, -2, -2,
+    },
+    {
+       0,  0,  0,  0,
+       1,  1,  1,  1,
+      -1, -1, -1, -1,
+       0,  0,  0,  0,
+    },
+  },
+  {
+    { 127 },
+    {
+       127,  127,  127,  127,
+        -1,   -1,   -1,   -1,
+      -128, -128, -128, -128,
+        -2,   -2,   -2,   -2,
+    },
+    {
+         0,    0,    0,    0,
+        -1,   -1,   -1,   -1,
+        -1,   -1,   -1,   -1,
+        -2,   -2,   -2,   -2,
+    },
+  },
+  {
+    { -128 },
+    {
+      -128, -128, -128, -128,
+         1,    1,    1,    1,
+       127,  127,  127,  127,
+         2,    2,    2,    2,
+    },
+    {
+         0,    0,    0,    0,
+         1,    1,    1,    1,
+       127,  127,  127,  127,
+         2,    2,    2,    2,
+    },
+  },
+};
+
+int16_t TEST_BINARY_DATA(int16_t, rem)[][3][N] =
+{
+  {
+    { 2 },
+    {
+       2,  2,  2,  2,
+       1,  1,  1,  1,
+      -1, -1, -1, -1,
+      -2, -2, -2, -2,
+    },
+    {
+       0,  0,  0,  0,
+       1,  1,  1,  1,
+      -1, -1, -1, -1,
+       0,  0,  0,  0,
+    },
+  },
+  {
+    { 32767 },
+    {
+       32767,  32767,  32767,  32767,
+          -1,     -1,     -1,     -1,
+      -32768, -32768, -32768, -32768,
+          -2,     -2,     -2,     -2,
+    },
+    {
+         0,    0,    0,    0,
+        -1,   -1,   -1,   -1,
+        -1,   -1,   -1,   -1,
+        -2,   -2,   -2,   -2,
+    },
+  },
+  {
+    { -32768 },
+    {
+      -32768, -32768, -32768, -32768,
+           1,      1,      1,      1,
+       32767,  32767,  32767,  32767,
+           2,      2,      2,      2,
+    },
+    {
+           0,      0,      0,      0,
+           1,      1,      1,      1,
+       32767,  32767,  32767,  32767,
+           2,      2,      2,      2,
+    },
+  },
+};
+
+int32_t TEST_BINARY_DATA(int32_t, rem)[][3][N] =
+{
+  {
+    { 2 },
+    {
+       2,  2,  2,  2,
+       1,  1,  1,  1,
+      -1, -1, -1, -1,
+      -2, -2, -2, -2,
+    },
+    {
+       0,  0,  0,  0,
+       1,  1,  1,  1,
+      -1, -1, -1, -1,
+       0,  0,  0,  0,
+    },
+  },
+  {
+    { 2147483647 },
+    {
+       2147483647,  2147483647,  2147483647,  2147483647,
+               -1,          -1,          -1,          -1,
+      -2147483648, -2147483648, -2147483648, -2147483648,
+               -2,          -2,          -2,          -2,
+    },
+    {
+         0,    0,    0,    0,
+        -1,   -1,   -1,   -1,
+        -1,   -1,   -1,   -1,
+        -2,   -2,   -2,   -2,
+    },
+  },
+  {
+    { -2147483648 },
+    {
+      -2147483648, -2147483648, -2147483648, -2147483648,
+                1,           1,           1,           1,
+       2147483647,  2147483647,  2147483647,  2147483647,
+                2,           2,           2,           2,
+    },
+    {
+                0,           0,           0,           0,
+                1,           1,           1,           1,
+       2147483647,  2147483647,  2147483647,  2147483647,
+                2,           2,           2,           2,
+    },
+  },
+};
+
+int64_t TEST_BINARY_DATA(int64_t, rem)[][3][N] =
+{
+  {
+    { 2 },
+    {
+       2,  2,  2,  2,
+       1,  1,  1,  1,
+      -1, -1, -1, -1,
+      -2, -2, -2, -2,
+    },
+    {
+       0,  0,  0,  0,
+       1,  1,  1,  1,
+      -1, -1, -1, -1,
+       0,  0,  0,  0,
+    },
+  },
+  {
+    { 9223372036854775807ll },
+    {
+        9223372036854775807ll,   9223372036854775807ll,   9223372036854775807ll,   9223372036854775807ll,
+                           -1,                      -1,                      -1,                      -1,
+      -9223372036854775808ull, -9223372036854775808ull, -9223372036854775808ull, -9223372036854775808ull,
+                           -2,                      -2,                      -2,                      -2,
+    },
+    {
+         0,    0,    0,    0,
+        -1,   -1,   -1,   -1,
+        -1,   -1,   -1,   -1,
+        -2,   -2,   -2,   -2,
+    },
+  },
+  {
+    { -9223372036854775808ull },
+    {
+      -9223372036854775808ull, -9223372036854775808ull, -9223372036854775808ull, -9223372036854775808ull,
+                            1,                       1,                       1,                       1,
+        9223372036854775807ll,   9223372036854775807ll,   9223372036854775807ll,   9223372036854775807ll,
+                            2,                       2,                       2,                       2,
+    },
+    {
+                           0,                      0,                      0,                      0,
+                           1,                      1,                      1,                      1,
+       9223372036854775807ll,  9223372036854775807ll,  9223372036854775807ll,  9223372036854775807ll,
+                           2,                      2,                      2,                      2,
+    },
+  },
+};
+
 #endif

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vrem-run-1-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vrem-run-1-i16.c
new file mode 100644 (file)
index 0000000..4320789
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vrem-run-1-i16.c
@@ -0,0 +1,15 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */
+
+#include "vx_binary.h"
+#include "vx_binary_data.h"
+
+#define T    int16_t
+#define NAME rem
+
+DEF_VX_BINARY_CASE_0_WRAP(T, %, NAME)
+
+#define TEST_DATA                        TEST_BINARY_DATA_WRAP(T, NAME)
+#define TEST_RUN(T, NAME, out, in, x, n) RUN_VX_BINARY_CASE_0_WRAP(T, NAME, out, in, x, n)
+
+#include "vx_binary_run.h"

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vrem-run-1-i32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vrem-run-1-i32.c
new file mode 100644 (file)
index 0000000..43a001b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vrem-run-1-i32.c
@@ -0,0 +1,15 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */
+
+#include "vx_binary.h"
+#include "vx_binary_data.h"
+
+#define T    int32_t
+#define NAME rem
+
+DEF_VX_BINARY_CASE_0_WRAP(T, %, NAME)
+
+#define TEST_DATA                        TEST_BINARY_DATA_WRAP(T, NAME)
+#define TEST_RUN(T, NAME, out, in, x, n) RUN_VX_BINARY_CASE_0_WRAP(T, NAME, out, in, x, n)
+
+#include "vx_binary_run.h"

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vrem-run-1-i64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vrem-run-1-i64.c
new file mode 100644 (file)
index 0000000..2e9b43a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vrem-run-1-i64.c
@@ -0,0 +1,15 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */
+
+#include "vx_binary.h"
+#include "vx_binary_data.h"
+
+#define T    int64_t
+#define NAME rem
+
+DEF_VX_BINARY_CASE_0_WRAP(T, %, NAME)
+
+#define TEST_DATA                        TEST_BINARY_DATA_WRAP(T, NAME)
+#define TEST_RUN(T, NAME, out, in, x, n) RUN_VX_BINARY_CASE_0_WRAP(T, NAME, out, in, x, n)
+
+#include "vx_binary_run.h"

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vrem-run-1-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vrem-run-1-i8.c
new file mode 100644 (file)
index 0000000..d4185c7
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vrem-run-1-i8.c
@@ -0,0 +1,15 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */
+
+#include "vx_binary.h"
+#include "vx_binary_data.h"
+
+#define T    int8_t
+#define NAME rem
+
+DEF_VX_BINARY_CASE_0_WRAP(T, %, NAME)
+
+#define TEST_DATA                        TEST_BINARY_DATA_WRAP(T, NAME)
+#define TEST_RUN(T, NAME, out, in, x, n) RUN_VX_BINARY_CASE_0_WRAP(T, NAME, out, in, x, n)
+
+#include "vx_binary_run.h"