s390 disasm-test: Add new opcodes from Principles of Ops 15th edition

Add opcodes: BDEPG, BEXTG, CLZF, CTZG, LXA[BHFGQ], LLXA[BHFGQ], VBLEND,
VGEM, VD, VDL, VEVAL, VR, VRL
Adjust prerequisite test (needs -march=arch15 now) and expected results.

Fix s390_irgen_VDx: M5 values with one or more reserved bits set do not
cause a specification exception. Found by disasm-test.

diff --git a/VEX/priv/guest_s390_toIR.c b/VEX/priv/guest_s390_toIR.c
index dabe39f268cdec85cee850321c6e29f64253979d..4bd3468a1bb1031b7c8b7f117bf1d435ab2942ca 100644 (file)
--- a/VEX/priv/guest_s390_toIR.c
+++ b/VEX/priv/guest_s390_toIR.c
@@ -18079,7 +18079,7 @@ static void
 s390_irgen_VDx(UChar v1, UChar v2, UChar v3, UChar m4, UChar m5,
                Bool is_signed, Bool do_remainder)
 {
-   s390_insn_assert((m5 & 7) == 0 && m4 >= 2 && m4 <= 4);
+   s390_insn_assert(m4 >= 2 && m4 <= 4);
 
    IRTemp  op1 = newTemp(Ity_V128);
    IRTemp  op2 = newTemp(Ity_V128);

diff --git a/none/tests/s390x/disasm-test/disasm-test.post.exp b/none/tests/s390x/disasm-test/disasm-test.post.exp
index 81756d885aa1ce7d0b42ddadf39590ae4b5dd3ec..ab3c93aa9e159383b91ef5620a6a981c95b5a6c8 100644 (file)
--- a/none/tests/s390x/disasm-test/disasm-test.post.exp
+++ b/none/tests/s390x/disasm-test/disasm-test.post.exp
@@ -1,6 +1,6 @@
 Looking for missed specification exceptions
-Total:  43103 tests generated
-Total:  43103 specification exceptions
+Total:  43957 tests generated
+Total:  43957 specification exceptions
 Looking for unexpected specification exceptions
-Total: 153961 tests generated
+Total: 154451 tests generated
 Total:      0 specification exceptions

diff --git a/none/tests/s390x/disasm-test/disasm-test.vgtest b/none/tests/s390x/disasm-test/disasm-test.vgtest
index 79c993c3d2966638678c4cdebb44639a7b0fe50a..147f63eda2796bdba855499efa07bdbeb8ac6965 100644 (file)
--- a/none/tests/s390x/disasm-test/disasm-test.vgtest
+++ b/none/tests/s390x/disasm-test/disasm-test.vgtest
@@ -7,9 +7,9 @@
 # kma   - Cannot express constraint that r3 must be different from r1 and r2
 # srnmb - The compile-time checkable constraint cannot be expressed in opcode.c
 #
-prereq: ./disasm-test --check-march=arch14
+prereq: ./disasm-test --check-march=arch15
 prog: /bin/true
-post: ./disasm-test --gcc-flags=-march=arch14 --all --exclude exrl kma srnmb --summary
+post: ./disasm-test --gcc-flags=-march=arch15 --all --exclude exrl kma srnmb --summary
 vgopts: -q
 stderr_filter:
 stderrB_filter:

diff --git a/none/tests/s390x/disasm-test/opcode.c b/none/tests/s390x/disasm-test/opcode.c
index bae4803d22dbd55c7e9c19b18be61f04db6101ff..0e41ab0c8611bfd5f25b7bc587cd0c391d2d9bdb 100644 (file)
--- a/none/tests/s390x/disasm-test/opcode.c
+++ b/none/tests/s390x/disasm-test/opcode.c
@@ -103,6 +103,7 @@
    mi1   --> miscellaneous-instruction-extensions facility 1
    mi2   --> miscellaneous-instruction-extensions facility 2
    mi3   --> miscellaneous-instruction-extensions facility 3
+   mi4   --> miscellaneous-instruction-extensions facility 4
    msa4  --> message-security-assist extension 4
    msa5  --> message-security-assist extension 5
    msa8  --> message-security-assist extension 8
@@ -115,7 +116,8 @@
    stfle --> STFLE facility
    vx    --> vector facility
    vxe   --> vector enhancements facility 1
-   vxe2  --> vector enhancements facility 2   implies vxe and vx
+   vxe2  --> vector enhancements facility 2
+   vxe3  --> vector enhancements facility 3
    vxd   --> vector packed decimal facility
 */
 
@@ -204,6 +206,9 @@ static const char *opcodes[] = {
    "ncrk    r1,r2,r3",          // mi3
    "ncgrk   r1,r2,r3",          // mi3
 
+   "bdepg   r1,r2,r3",          // mi4
+   "bextg   r1,r2,r3",          // mi4
+
    // balr   not implemented
    // bal    not implemented
 
@@ -411,6 +416,9 @@ static const char *opcodes[] = {
 
    "cpya   a1,a2",
 
+   "clzg   r1,r2",     // mi4
+   "ctzg   r1,r2",     // mi4
+
    "dr     r1:{0,2,4,6,8,10,12,14},r2",
    "d      r1:{0,2,4,6,8,10,12,14},d12(x2,b2)",
 
@@ -560,6 +568,12 @@ static const char *opcodes[] = {
 
    "lfhat  r1,d20(x2,b2)",      // lat
 
+   "lxab   r1,d20(x2,b2)",      // mi4
+   "lxah   r1,d20(x2,b2)",      // mi4
+   "lxaf   r1,d20(x2,b2)",      // mi4
+   "lxag   r1,d20(x2,b2)",      // mi4
+   "lxaq   r1,d20(x2,b2)",      // mi4
+
    "llgfr  r1,r2",
    "llgf   r1,d20(x2,b2)",
 
@@ -593,6 +607,12 @@ static const char *opcodes[] = {
    "llilh  r1,i2:u16",
    "llill  r1,i2:u16",
 
+   "llxab   r1,d20(x2,b2)",     // mi4
+   "llxah   r1,d20(x2,b2)",     // mi4
+   "llxaf   r1,d20(x2,b2)",     // mi4
+   "llxag   r1,d20(x2,b2)",     // mi4
+   "llxaq   r1,d20(x2,b2)",     // mi4
+
    "llgtr  r1,r2",
    "llgt   r1,d20(x2,b2)",
 
@@ -1187,9 +1207,11 @@ static const char *opcodes[] = {
    // all opcodes require VX facility
 
    "vbperm  v1,v2,v3",                          // vxe
+   "vblend  v1,v2,v3,v4,m5:{0..4}",             // vxe3
    "vgef    v1,d12(v2,b2),m3:{0,1,2,3}",
    "vgeg    v1,d12(v2,b2),m3:{0,1}",
    "vgbm    v1,i2:u16",
+   "vgem    v1,v2,m3:{0..4}",                   // vxe3
    "vgm     v1,i2:u8,i3:u8,m4:{0..3}",
    "vl      v1,d12(x2,b2),m3",
    "vlr     v1,v2",
@@ -1267,6 +1289,9 @@ static const char *opcodes[] = {
    "vchl    v1,v2,v3,m4:{0..4},m5",
    "vclz    v1,v2,m3:{0..4}",
    "vctz    v1,v2,m3:{0..4}",
+   "vd      v1,v2,v3,m4:{2,3,4},m5",             // vxe3
+   "vdl     v1,v2,v3,m4:{2,3,4},m5",             // vxe3
+   "veval   v1,v2,v3,v4,i5:u8",                  // vxe3
    "vx      v1,v2,v3",
    "vgfm    v1,v2,v3,m4:{0..3}",
    "vgfma   v1,v2,v3,v4,m5:{0..3}",
@@ -1296,6 +1321,8 @@ static const char *opcodes[] = {
    "vnx     v1,v2,v3",                           // vxe
    "vo      v1,v2,v3",
    "voc     v1,v2,v3",                           // vxe
+   "vr      v1,v2,v3,m4:{2,3,4},m5",             // vxe3
+   "vrl     v1,v2,v3,m4:{2,3,4},m5",             // vxe3
    "vpopct  v1,v2,m3:{0..3}",
    "verllv  v1,v2,v3,m4:{0..3}",
    "verll   v1,v3,d12(b2),m4:{0..3}",