arm64: dts: ti: k3-j721s2-main: Add DSI1

Add the second DSI instance and its corresponding phy to the main domain
include file.

Signed-off-by: Dominik Haller <d.haller@phytec.de>
Reviewed-by: Beleswar Padhi <b-padhi@ti.com>
Link: https://patch.msgid.link/20260320212349.420951-5-d.haller@phytec.de
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>

diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi
index 80c51b11ac9fa07d928f1421ab871b262a7be57e..80a32c451d1bc5caca8730b367fbd30657ea8c1f 100644 (file)
--- a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi
@@ -1815,6 +1815,19 @@
                status = "disabled";
        };
 
+       dphy_tx1: phy@4481000 {
+               compatible = "ti,j721e-dphy";
+               reg = <0x00 0x04481000 0x00 0x00001000>;
+               clocks = <&k3_clks 364 8>, <&k3_clks 364 14>;
+               clock-names = "psm", "pll_ref";
+               #phy-cells = <0>;
+               power-domains = <&k3_pds 364 TI_SCI_PD_EXCLUSIVE>;
+               assigned-clocks = <&k3_clks 364 14>;
+               assigned-clock-parents = <&k3_clks 364 15>;
+               assigned-clock-rates = <19200000>;
+               status = "disabled";
+       };
+
        dsi0: dsi@4800000 {
                compatible = "ti,j721e-dsi";
                reg = <0x00 0x04800000 0x00 0x00100000>,
@@ -1841,6 +1854,32 @@
                };
        };
 
+       dsi1: dsi@4900000 {
+               compatible = "ti,j721e-dsi";
+               reg = <0x00 0x04900000 0x00 0x00100000>,
+                     <0x00 0x04720000 0x00 0x00000100>;
+               clocks = <&k3_clks 155 4>, <&k3_clks 155 1>;
+               clock-names = "dsi_p_clk", "dsi_sys_clk";
+               power-domains = <&k3_pds 155 TI_SCI_PD_EXCLUSIVE>;
+               interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
+               phys = <&dphy_tx1>;
+               phy-names = "dphy";
+               status = "disabled";
+
+               dsi1_ports: ports {
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+
+                       port@0 {
+                               reg = <0>;
+                       };
+
+                       port@1 {
+                               reg = <1>;
+                       };
+               };
+       };
+
        dss: dss@4a00000 {
                compatible = "ti,j721e-dss";
                reg = <0x00 0x04a00000 0x00 0x10000>, /* common_m */