drm/amd/ras: Add table reset func for pmfw eeprom

add table reset func for pmfw eeprom, add smu eeprom control
structure

Signed-off-by: Gangliang Xie <ganglxie@amd.com>
Reviewed-by: Tao Zhou <tao.zhou1@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/ras/rascore/ras.h b/drivers/gpu/drm/amd/ras/rascore/ras.h
index 07ef4e0d53f6b9dc9f20294a8a74ae7719e535a6..4ceb72d24e3556f7ffd90bebc2c9b52142ba1a7a 100644 (file)
--- a/drivers/gpu/drm/amd/ras/rascore/ras.h
+++ b/drivers/gpu/drm/amd/ras/rascore/ras.h
@@ -313,6 +313,7 @@ struct ras_core_context {
 
        bool ras_eeprom_supported;
        struct ras_eeprom_control ras_eeprom;
+       struct ras_fw_eeprom_control ras_fw_eeprom;
 
        struct ras_psp ras_psp;
        struct ras_umc ras_umc;

diff --git a/drivers/gpu/drm/amd/ras/rascore/ras_cmd.c b/drivers/gpu/drm/amd/ras/rascore/ras_cmd.c
index 94e6d7420d94eb45a1c4da0478fbddfb348b2cf1..4f89810d85a15eff2e2d2f11a423634b0ee68199 100644 (file)
--- a/drivers/gpu/drm/amd/ras/rascore/ras_cmd.c
+++ b/drivers/gpu/drm/amd/ras/rascore/ras_cmd.c
@@ -146,8 +146,13 @@ static int ras_cmd_clear_bad_page_info(struct ras_core_context *ras_core,
        if (cmd->input_size != sizeof(struct ras_cmd_dev_handle))
                return RAS_CMD__ERROR_INVALID_INPUT_SIZE;
 
-       if (ras_eeprom_reset_table(ras_core))
-               return RAS_CMD__ERROR_GENERIC;
+       if (ras_fw_eeprom_supported(ras_core)) {
+               if (ras_fw_eeprom_reset_table(ras_core))
+                       return RAS_CMD__ERROR_GENERIC;
+       } else {
+               if (ras_eeprom_reset_table(ras_core))
+                       return RAS_CMD__ERROR_GENERIC;
+       }
 
        if (ras_umc_clean_badpage_data(ras_core))
                return RAS_CMD__ERROR_GENERIC;

diff --git a/drivers/gpu/drm/amd/ras/rascore/ras_eeprom_fw.c b/drivers/gpu/drm/amd/ras/rascore/ras_eeprom_fw.c
index f880fc49477da0c880760e49e871bb05d813c765..ae63e7394829a0c79adc421f45d1bcd7838dadb3 100644 (file)
--- a/drivers/gpu/drm/amd/ras/rascore/ras_eeprom_fw.c
+++ b/drivers/gpu/drm/amd/ras/rascore/ras_eeprom_fw.c
@@ -161,3 +161,32 @@ int ras_fw_erase_ras_table(struct ras_core_context *ras_core,
        return sys_func->mp1_send_eeprom_msg(ras_core,
                        RAS_SMU_EraseRasTable, 0, result);
 }
+
+int ras_fw_eeprom_reset_table(struct ras_core_context *ras_core)
+{
+       struct ras_fw_eeprom_control *control = &ras_core->ras_fw_eeprom;
+       u32 erase_res = 0;
+       int res;
+
+       mutex_lock(&control->ras_tbl_mutex);
+
+       res = ras_fw_erase_ras_table(ras_core, &erase_res);
+       if (res || erase_res) {
+               RAS_DEV_WARN(ras_core->dev, "RAS EEPROM reset failed, res:%d result:%d",
+                                                                       res, erase_res);
+               if (!res)
+                       res = -EIO;
+       }
+
+       control->ras_num_recs = 0;
+       control->bad_channel_bitmap = 0;
+       ras_core_event_notify(ras_core, RAS_EVENT_ID__UPDATE_BAD_PAGE_NUM,
+               &control->ras_num_recs);
+       ras_core_event_notify(ras_core, RAS_EVENT_ID__UPDATE_BAD_CHANNEL_BITMAP,
+               &control->bad_channel_bitmap);
+       control->update_channel_flag = false;
+
+       mutex_unlock(&control->ras_tbl_mutex);
+
+       return res;
+}

diff --git a/drivers/gpu/drm/amd/ras/rascore/ras_eeprom_fw.h b/drivers/gpu/drm/amd/ras/rascore/ras_eeprom_fw.h
index 46f45e82a3f3a5347f49b19b4d15b42ee84bf4eb..a1003db3c33ba43a87140694a8512fc30208d1e7 100644 (file)
--- a/drivers/gpu/drm/amd/ras/rascore/ras_eeprom_fw.h
+++ b/drivers/gpu/drm/amd/ras/rascore/ras_eeprom_fw.h
@@ -24,6 +24,31 @@
 #ifndef __RAS_EEPROM_FW_H__
 #define __RAS_EEPROM_FW_H__
 
+struct ras_fw_eeprom_control {
+       uint32_t version;
+       /* record threshold */
+       int record_threshold_config;
+       uint32_t record_threshold_count;
+       bool update_channel_flag;
+
+       /* Number of records in the table.
+        */
+       u32 ras_num_recs;
+
+       /* Maximum possible number of records
+        * we could store, i.e. the maximum capacity
+        * of the table.
+        */
+       u32 ras_max_record_count;
+
+       /* Protect table access via this mutex.
+        */
+       struct mutex ras_tbl_mutex;
+
+       /* Record channel info which occurred bad pages
+        */
+       u32 bad_channel_bitmap;
+};
 
 void ras_fw_init_feature_flags(struct ras_core_context *ras_core);
 bool ras_fw_eeprom_supported(struct ras_core_context *ras_core);
@@ -41,5 +66,6 @@ int ras_fw_get_badpage_ipid(struct ras_core_context *ras_core,
                                    uint16_t index, uint64_t *ipid);
 int ras_fw_erase_ras_table(struct ras_core_context *ras_core,
                                   uint32_t *result);
+int ras_fw_eeprom_reset_table(struct ras_core_context *ras_core);
 
 #endif