arm: Don't reject early mov?fcc patterns that we might be able to handle

The define_expand patterns for movdfcc, movsfcc and movhfcc had overly
tight contstraints that could cause the compiler to reject these
patterns when re-ordering the operands could lead to a successful
match.  Relax the initial predicate test and rely on the test after
arm_validize_comparison has run to determine whether this is something
we can support.  This fixes some test failures which were introduced
in the fix for PR118460

gcc/ChangeLog:

	PR target/118460
	* config/arm/arm.md (movhfcc): Use expandable_comparison_operator.
	(movsfcc, movdfcc): Likewise.

diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md
index 422ae549b65bf1e85bffd8e79c3fba508bb81cd0..1517d5d6b50a88a50e0cd9fd8e7d80b440309fde 100644 (file)
--- a/gcc/config/arm/arm.md
+++ b/gcc/config/arm/arm.md
@@ -8350,7 +8350,7 @@
 
 (define_expand "movhfcc"
   [(set (match_operand:HF 0 "s_register_operand")
-       (if_then_else:HF (match_operand 1 "arm_cond_move_operator")
+       (if_then_else:HF (match_operand 1 "expandable_comparison_operator")
                         (match_operand:HF 2 "s_register_operand")
                         (match_operand:HF 3 "s_register_operand")))]
   "TARGET_VFP_FP16INST"
@@ -8372,7 +8372,7 @@
 
 (define_expand "movsfcc"
   [(set (match_operand:SF 0 "s_register_operand")
-       (if_then_else:SF (match_operand 1 "arm_cond_move_operator")
+       (if_then_else:SF (match_operand 1 "expandable_comparison_operator")
                         (match_operand:SF 2 "s_register_operand")
                         (match_operand:SF 3 "s_register_operand")))]
   "TARGET_32BIT && TARGET_HARD_FLOAT"
@@ -8394,7 +8394,7 @@
 
 (define_expand "movdfcc"
   [(set (match_operand:DF 0 "s_register_operand")
-       (if_then_else:DF (match_operand 1 "arm_cond_move_operator")
+       (if_then_else:DF (match_operand 1 "expandable_comparison_operator")
                         (match_operand:DF 2 "s_register_operand")
                         (match_operand:DF 3 "s_register_operand")))]
   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"