unsigned int ofs = sai->soc_data->reg_offset;
u32 val_cr2 = 0, val_cr4 = 0;
+ if (sai->is_bit_clock_swap)
+ val_cr2 |= FSL_SAI_CR2_BCS;
+
if (!sai->is_lsb_first)
val_cr4 |= FSL_SAI_CR4_MF;
}
regmap_update_bits(sai->regmap, FSL_SAI_xCR2(tx, ofs),
- FSL_SAI_CR2_BCP | FSL_SAI_CR2_BCD_MSTR, val_cr2);
+ FSL_SAI_CR2_BCS | FSL_SAI_CR2_BCP | FSL_SAI_CR2_BCD_MSTR,
+ val_cr2);
regmap_update_bits(sai->regmap, FSL_SAI_xCR4(tx, ofs),
FSL_SAI_CR4_MF | FSL_SAI_CR4_FSE |
FSL_SAI_CR4_FSP | FSL_SAI_CR4_FSD_MSTR, val_cr4);
sai->soc_data = of_device_get_match_data(dev);
sai->is_lsb_first = of_property_read_bool(np, "lsb-first");
+ sai->is_bit_clock_swap = of_property_read_bool(np, "fsl,sai-bit-clock-swap");
base = devm_platform_get_and_ioremap_resource(pdev, 0, &sai->res);
if (IS_ERR(base))
/* SAI Transmit and Receive Configuration 2 Register */
#define FSL_SAI_CR2_SYNC BIT(30)
+#define FSL_SAI_CR2_BCS BIT(29)
#define FSL_SAI_CR2_BCI BIT(28)
#define FSL_SAI_CR2_MSEL_MASK (0x3 << 26)
#define FSL_SAI_CR2_MSEL_BUS 0
struct fsl_sai_dl_cfg *dl_cfg;
unsigned int dl_cfg_cnt;
bool mclk_direction_output;
+ bool is_bit_clock_swap;
unsigned int mclk_id[2];
unsigned int mclk_streams;