clk: renesas: r8a08g045: Check the source of the CPU PLL settings

On the RZ/G3S SoC, the CPU PLL settings can be set and retrieved through
the CPG_PLL1_CLK1 and CPG_PLL1_CLK2 registers.  However, these settings
are applied only when CPG_PLL1_SETTING.SEL_PLL1 is set to 0.
Otherwise, the CPU PLL operates at the default frequency of 1.1 GHz.
Hence add support to the PLL driver for returning the 1.1 GHz frequency
when the CPU PLL is configured with the default frequency.

Fixes: 01eabef547e6 ("clk: renesas: rzg2l: Add support for RZ/G3S PLL")
Fixes: de60a3ebe410 ("clk: renesas: Add minimal boot support for RZ/G3S SoC")
Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20250115142059.1833063-1-claudiu.beznea.uj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

diff --git a/drivers/clk/renesas/r9a08g045-cpg.c b/drivers/clk/renesas/r9a08g045-cpg.c
index bc44e08e7eb9fb2d4ae407b122fe323124c14f91..4035f3443598e996a3b297d22d714b70d7605ffc 100644 (file)
--- a/drivers/clk/renesas/r9a08g045-cpg.c
+++ b/drivers/clk/renesas/r9a08g045-cpg.c
@@ -51,7 +51,7 @@
 #define G3S_SEL_SDHI2          SEL_PLL_PACK(G3S_CPG_SDHI_DSEL, 8, 2)
 
 /* PLL 1/4/6 configuration registers macro. */
-#define G3S_PLL146_CONF(clk1, clk2)    ((clk1) << 22 | (clk2) << 12)
+#define G3S_PLL146_CONF(clk1, clk2, setting)   ((clk1) << 22 | (clk2) << 12 | (setting))
 
 #define DEF_G3S_MUX(_name, _id, _conf, _parent_names, _mux_flags, _clk_flags) \
        DEF_TYPE(_name, _id, CLK_TYPE_MUX, .conf = (_conf), \
@@ -134,7 +134,8 @@ static const struct cpg_core_clk r9a08g045_core_clks[] __initconst = {
 
        /* Internal Core Clocks */
        DEF_FIXED(".osc_div1000", CLK_OSC_DIV1000, CLK_EXTAL, 1, 1000),
-       DEF_G3S_PLL(".pll1", CLK_PLL1, CLK_EXTAL, G3S_PLL146_CONF(0x4, 0x8)),
+       DEF_G3S_PLL(".pll1", CLK_PLL1, CLK_EXTAL, G3S_PLL146_CONF(0x4, 0x8, 0x100),
+                   1100000000UL),
        DEF_FIXED(".pll2", CLK_PLL2, CLK_EXTAL, 200, 3),
        DEF_FIXED(".pll3", CLK_PLL3, CLK_EXTAL, 200, 3),
        DEF_FIXED(".pll4", CLK_PLL4, CLK_EXTAL, 100, 3),

diff --git a/drivers/clk/renesas/rzg2l-cpg.c b/drivers/clk/renesas/rzg2l-cpg.c
index 6e4a51427bd2b0ae7b07cae3bef6ffd583c87d43..91928db411dcd139ad495295e19673869b866c48 100644 (file)
--- a/drivers/clk/renesas/rzg2l-cpg.c
+++ b/drivers/clk/renesas/rzg2l-cpg.c
@@ -51,6 +51,7 @@
 #define RZG3S_DIV_M            GENMASK(25, 22)
 #define RZG3S_DIV_NI           GENMASK(21, 13)
 #define RZG3S_DIV_NF           GENMASK(12, 1)
+#define RZG3S_SEL_PLL          BIT(0)
 
 #define CLK_ON_R(reg)          (reg)
 #define CLK_MON_R(reg)         (0x180 + (reg))
@@ -60,6 +61,7 @@
 #define GET_REG_OFFSET(val)            ((val >> 20) & 0xfff)
 #define GET_REG_SAMPLL_CLK1(val)       ((val >> 22) & 0xfff)
 #define GET_REG_SAMPLL_CLK2(val)       ((val >> 12) & 0xfff)
+#define GET_REG_SAMPLL_SETTING(val)    ((val) & 0xfff)
 
 #define CPG_WEN_BIT            BIT(16)
 
@@ -943,6 +945,7 @@ rzg2l_cpg_sipll5_register(const struct cpg_core_clk *core,
 
 struct pll_clk {
        struct clk_hw hw;
+       unsigned long default_rate;
        unsigned int conf;
        unsigned int type;
        void __iomem *base;
@@ -980,12 +983,19 @@ static unsigned long rzg3s_cpg_pll_clk_recalc_rate(struct clk_hw *hw,
 {
        struct pll_clk *pll_clk = to_pll(hw);
        struct rzg2l_cpg_priv *priv = pll_clk->priv;
-       u32 nir, nfr, mr, pr, val;
+       u32 nir, nfr, mr, pr, val, setting;
        u64 rate;
 
        if (pll_clk->type != CLK_TYPE_G3S_PLL)
                return parent_rate;
 
+       setting = GET_REG_SAMPLL_SETTING(pll_clk->conf);
+       if (setting) {
+               val = readl(priv->base + setting);
+               if (val & RZG3S_SEL_PLL)
+                       return pll_clk->default_rate;
+       }
+
        val = readl(priv->base + GET_REG_SAMPLL_CLK1(pll_clk->conf));
 
        pr = 1 << FIELD_GET(RZG3S_DIV_P, val);
@@ -1038,6 +1048,7 @@ rzg2l_cpg_pll_clk_register(const struct cpg_core_clk *core,
        pll_clk->base = priv->base;
        pll_clk->priv = priv;
        pll_clk->type = core->type;
+       pll_clk->default_rate = core->default_rate;
 
        ret = devm_clk_hw_register(dev, &pll_clk->hw);
        if (ret)

diff --git a/drivers/clk/renesas/rzg2l-cpg.h b/drivers/clk/renesas/rzg2l-cpg.h
index af09c74d596a603838a09f3d6a79402efd0be560..b6eece5ffa20f415f951f8dbd9af78fc9af0797b 100644 (file)
--- a/drivers/clk/renesas/rzg2l-cpg.h
+++ b/drivers/clk/renesas/rzg2l-cpg.h
@@ -104,7 +104,10 @@ struct cpg_core_clk {
        const struct clk_div_table *dtable;
        const u32 *mtable;
        const unsigned long invalid_rate;
-       const unsigned long max_rate;
+       union {
+               const unsigned long max_rate;
+               const unsigned long default_rate;
+       };
        const char * const *parent_names;
        notifier_fn_t notifier;
        u32 flag;
@@ -146,8 +149,9 @@ enum clk_types {
        DEF_TYPE(_name, _id, _type, .parent = _parent)
 #define DEF_SAMPLL(_name, _id, _parent, _conf) \
        DEF_TYPE(_name, _id, CLK_TYPE_SAM_PLL, .parent = _parent, .conf = _conf)
-#define DEF_G3S_PLL(_name, _id, _parent, _conf) \
-       DEF_TYPE(_name, _id, CLK_TYPE_G3S_PLL, .parent = _parent, .conf = _conf)
+#define DEF_G3S_PLL(_name, _id, _parent, _conf, _default_rate) \
+       DEF_TYPE(_name, _id, CLK_TYPE_G3S_PLL, .parent = _parent, .conf = _conf, \
+                .default_rate = _default_rate)
 #define DEF_INPUT(_name, _id) \
        DEF_TYPE(_name, _id, CLK_TYPE_IN)
 #define DEF_FIXED(_name, _id, _parent, _mult, _div) \