arm64: dts: renesas: r8a77960: Describe PCIe root ports

Add nodes which describe the root ports in the PCIe controller DT nodes.
This can be used together with the pwrctrl driver to control clock and
power supply to a PCIe slot.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://patch.msgid.link/20260118135038.8033-3-marek.vasut+renesas@mailbox.org
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

diff --git a/arch/arm64/boot/dts/renesas/r8a77960.dtsi b/arch/arm64/boot/dts/renesas/r8a77960.dtsi
index e64c7b1aebc4732418ae346d29907d118f4898f2..ad36aa8e75435c3d85cc7c979b513bf4177db2dd 100644 (file)
--- a/arch/arm64/boot/dts/renesas/r8a77960.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a77960.dtsi
@@ -2619,6 +2619,16 @@
                        iommu-map = <0 &ipmmu_hc 0 1>;
                        iommu-map-mask = <0>;
                        status = "disabled";
+
+                       /* PCIe bridge, Root Port */
+                       pciec0_rp: pci@0,0 {
+                               #address-cells = <3>;
+                               #size-cells = <2>;
+                               reg = <0x0 0x0 0x0 0x0 0x0>;
+                               compatible = "pciclass,0604";
+                               device_type = "pci";
+                               ranges;
+                       };
                };
 
                pciec1: pcie@ee800000 {
@@ -2648,6 +2658,16 @@
                        iommu-map = <0 &ipmmu_hc 1 1>;
                        iommu-map-mask = <0>;
                        status = "disabled";
+
+                       /* PCIe bridge, Root Port */
+                       pciec1_rp: pci@0,0 {
+                               #address-cells = <3>;
+                               #size-cells = <2>;
+                               reg = <0x0 0x0 0x0 0x0 0x0>;
+                               compatible = "pciclass,0604";
+                               device_type = "pci";
+                               ranges;
+                       };
                };
 
                imr-lx4@fe860000 {