Removed unused code that has been lying around since the major refactoring

of this file a couple of years back.

git-svn-id: svn://svn.valgrind.org/vex/trunk@3168

diff --git a/VEX/priv/guest_amd64_toIR.c b/VEX/priv/guest_amd64_toIR.c
index d34a1383b5a387425ff4d36f6a9287f10c722924..908b84ecaa8c4e9c3170bc92627a65ff97f68b99 100644 (file)
--- a/VEX/priv/guest_amd64_toIR.c
+++ b/VEX/priv/guest_amd64_toIR.c
@@ -31685,193 +31685,7 @@ DisResult disInstr_AMD64_WRK (
    else
       goto decode_success; /* \o/ */
 
-#if 0 /* XYZZY */
 
-   /* ---------------------------------------------------- */
-   /* --- The SSE/SSE2 decoder.                        --- */
-   /* ---------------------------------------------------- */
-
-   /* What did I do to deserve SSE ?  Perhaps I was really bad in a
-      previous life? */
-
-   /* Note, this doesn't handle SSE3 right now.  All amd64s support
-      SSE2 as a minimum so there is no point distinguishing SSE1 vs
-      SSE2. */
-
-   insn = &guest_code[delta];
-
-   /* FXSAVE is spuriously at the start here only because it is
-      thusly placed in guest-x86/toIR.c. */
-
-   /* ------ SSE decoder main ------ */
-
-   /* ---------------------------------------------------- */
-   /* --- end of the SSE decoder.                      --- */
-   /* ---------------------------------------------------- */
-
-   /* ---------------------------------------------------- */
-   /* --- start of the SSE2 decoder.                   --- */
-   /* ---------------------------------------------------- */
-
-   /* ---------------------------------------------------- */
-   /* --- end of the SSE/SSE2 decoder.                 --- */
-   /* ---------------------------------------------------- */
-
-   /* ---------------------------------------------------- */
-   /* --- start of the SSE3 decoder.                   --- */
-   /* ---------------------------------------------------- */
-
-   /* ---------------------------------------------------- */
-   /* --- end of the SSE3 decoder.                     --- */
-   /* ---------------------------------------------------- */
-
-   /* ---------------------------------------------------- */
-   /* --- start of the SSSE3 decoder.                  --- */
-   /* ---------------------------------------------------- */
-
-   /* ---------------------------------------------------- */
-   /* --- end of the SSSE3 decoder.                    --- */
-   /* ---------------------------------------------------- */
-
-   /* ---------------------------------------------------- */
-   /* --- start of the SSE4 decoder                    --- */
-   /* ---------------------------------------------------- */
-
-   /* ---------------------------------------------------- */
-   /* --- end of the SSE4 decoder                      --- */
-   /* ---------------------------------------------------- */
-
-   /*after_sse_decoders:*/
-
-   /* Get the primary opcode. */
-   opc = getUChar(delta); delta++;
-
-   /* We get here if the current insn isn't SSE, or this CPU doesn't
-      support SSE. */
-
-   switch (opc) {
-
-   /* ------------------------ Control flow --------------- */
-
-   /* ------------------------ CWD/CDQ -------------------- */
-
-   /* ------------------------ FPU ops -------------------- */
-
-   /* ------------------------ INT ------------------------ */
-
-   case 0xCD: { /* INT imm8 */
-      IRJumpKind jk = Ijk_Boring;
-      if (have66orF2orF3(pfx)) goto decode_failure;
-      d64 = getUChar(delta); delta++;
-      switch (d64) {
-         case 32: jk = Ijk_Sys_int32; break;
-         default: goto decode_failure;
-      }
-      guest_RIP_next_mustcheck = True;
-      guest_RIP_next_assumed = guest_RIP_bbstart + delta;
-      jmp_lit(jk, guest_RIP_next_assumed);
-      /* It's important that all ArchRegs carry their up-to-date value
-         at this point.  So we declare an end-of-block here, which
-         forces any TempRegs caching ArchRegs to be flushed. */
-      vassert(dres.whatNext == Dis_StopHere);
-      DIP("int $0x%02x\n", (UInt)d64);
-      break;
-   }
-
-   /* ------------------------ Jcond, byte offset --------- */
-
-   /* ------------------------ IMUL ----------------------- */
-
-   /* ------------------------ MOV ------------------------ */
-
-   /* ------------------------ MOVx ------------------------ */
-
-   /* ------------------------ opl imm, A ----------------- */
-
-   /* ------------------------ opl Ev, Gv ----------------- */
-
-   /* ------------------------ opl Gv, Ev ----------------- */
-
-   /* ------------------------ POP ------------------------ */
-
-   /* ------------------------ PUSH ----------------------- */
-
-   /* ------ AE: SCAS variants ------ */
-
-   /* ------ A6, A7: CMPS variants ------ */
-
-   /* ------ AA, AB: STOS variants ------ */
-
-   /* ------ A4, A5: MOVS variants ------ */
-
-   /* ------------------------ XCHG ----------------------- */
-
-   /* ------------------------ IN / OUT ----------------------- */
- 
-   /* ------------------------ (Grp1 extensions) ---------- */
-
-   /* ------------------------ (Grp2 extensions) ---------- */
-
-   /* ------------------------ (Grp3 extensions) ---------- */
-
-   /* ------------------------ (Grp4 extensions) ---------- */
-
-   /* ------------------------ (Grp5 extensions) ---------- */
-
-   /* ------------------------ Escapes to 2-byte opcodes -- */
-
-   case 0x0F: {
-      opc = getUChar(delta); delta++;
-      switch (opc) {
-
-      /* =-=-=-=-=-=-=-=-=- Grp8 =-=-=-=-=-=-=-=-=-=-=-= */
-
-      /* =-=-=-=-=-=-=-=-=- BSF/BSR -=-=-=-=-=-=-=-=-=-= */
-
-      /* =-=-=-=-=-=-=-=-=- BSWAP -=-=-=-=-=-=-=-=-=-=-= */
-
-      /* =-=-=-=-=-=-=-=-=- BT/BTS/BTR/BTC =-=-=-=-=-=-= */
-
-      /* =-=-=-=-=-=-=-=-=- CMOV =-=-=-=-=-=-=-=-=-=-=-= */
-
-      /* =-=-=-=-=-=-=-=-=- CMPXCHG -=-=-=-=-=-=-=-=-=-= */
-
-      /* =-=-=-=-=-=-=-=-=- CPUID -=-=-=-=-=-=-=-=-=-=-= */
-
-      /* =-=-=-=-=-=-=-=-=- MOVZX, MOVSX =-=-=-=-=-=-=-= */
-
-      /* =-=-=-=-=-=-=-=-=- MUL/IMUL =-=-=-=-=-=-=-=-=-= */
-
-      /* =-=-=-=-=-=-=-=-=- NOPs =-=-=-=-=-=-=-=-=-=-=-= */
-
-      /* =-=-=-=-=-=-=-=-=- Jcond d32 -=-=-=-=-=-=-=-=-= */
-
-      /* =-=-=-=-=-=-=-=-=- PREFETCH =-=-=-=-=-=-=-=-=-= */
-
-      /* =-=-=-=-=-=-=-=-=- RDTSC -=-=-=-=-=-=-=-=-=-=-= */
-
-      /* =-=-=-=-=-=-=-=-=- SETcc Eb =-=-=-=-=-=-=-=-=-= */
-
-      /* =-=-=-=-=-=-=-=-=- SHLD/SHRD -=-=-=-=-=-=-=-=-= */
-
-      /* =-=-=-=-=-=-=-=-=- SYSCALL -=-=-=-=-=-=-=-=-=-= */
-
-      /* =-=-=-=-=-=-=-=-=- XADD -=-=-=-=-=-=-=-=-=-= */
-
-      /* =-=-=-=-=-=-=-=-=- SGDT and SIDT =-=-=-=-=-=-=-=-=-=-= */
-
-      /* =-=-=-=-=-=-=-=-=- unimp2 =-=-=-=-=-=-=-=-=-=-= */
-
-      default:
-         goto decode_failure;
-   } /* switch (opc) for the 2-byte opcodes */
-   goto decode_success;
-   } /* case 0x0F: of primary opcode */
-
-   /* ------------------------ ??? ------------------------ */
-#endif /* XYZZY */
-  
-     //default:
   decode_failure:
    /* All decode failures end up here. */
    if (sigill_diag) {
@@ -31917,7 +31731,6 @@ DisResult disInstr_AMD64_WRK (
    *expect_CAS = False;
    return dres;
 
-   //   } /* switch (opc) for the main (primary) opcode switch. */
 
   decode_success:
    /* All decode successes end up here. */