drm/msm/registers: Generate _HI/LO builders for reg64

[ Upstream commit 60e9f776b7932d67c88e8475df7830cb9cdf3154 ]

The upstream mesa copy of the GPU regs has shifted more things to reg64
instead of seperate 32b HI/LO reg32's.  This works better with the "new-
style" c++ builders that mesa has been migrating to for a6xx+ (to better
handle register shuffling between gens), but it leaves the C builders
with missing _HI/LO builders.

So handle the special case of reg64, automatically generating the
missing _HI/LO builders.

Signed-off-by: Rob Clark <robin.clark@oss.qualcomm.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Patchwork: https://patchwork.freedesktop.org/patch/673559/
Signed-off-by: Sasha Levin <sashal@kernel.org>

diff --git a/drivers/gpu/drm/msm/registers/gen_header.py b/drivers/gpu/drm/msm/registers/gen_header.py
index a409404627c7180d5b0626f0ce6255d7d0df5113..6a6f9e52b11f7d4f7bcc09a10d04c287c86ea985 100644 (file)
--- a/drivers/gpu/drm/msm/registers/gen_header.py
+++ b/drivers/gpu/drm/msm/registers/gen_header.py
@@ -150,6 +150,7 @@ class Bitset(object):
        def __init__(self, name, template):
                self.name = name
                self.inline = False
+               self.reg = None
                if template:
                        self.fields = template.fields[:]
                else:
@@ -256,6 +257,11 @@ class Bitset(object):
        def dump(self, prefix=None):
                if prefix == None:
                        prefix = self.name
+               if self.reg and self.reg.bit_size == 64:
+                       print("static inline uint32_t %s_LO(uint32_t val)\n{" % prefix)
+                       print("\treturn val;\n}")
+                       print("static inline uint32_t %s_HI(uint32_t val)\n{" % prefix)
+                       print("\treturn val;\n}")
                for f in self.fields:
                        if f.name:
                                name = prefix + "_" + f.name
@@ -620,6 +626,7 @@ class Parser(object):
 
                self.current_reg = Reg(attrs, self.prefix(variant), self.current_array, bit_size)
                self.current_reg.bitset = self.current_bitset
+               self.current_bitset.reg = self.current_reg
 
                if len(self.stack) == 1:
                        self.file.append(self.current_reg)