media: ccs-pll: Correct the upper limit of maximum op_pre_pll_clk_div

commit f639494db450770fa30d6845d9c84b9cb009758f upstream.

The PLL calculator does a search of the PLL configuration space for all
valid OP pre-PLL clock dividers. The maximum did not take into account the
CCS PLL flag CCS_PLL_FLAG_EXT_IP_PLL_DIVIDER in which case also odd PLL
dividers (other than 1) are valid. Do that now.

Fixes: 4e1e8d240dff ("media: ccs-pll: Add support for extended input PLL clock divider")
Cc: stable@vger.kernel.org
Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Hans Verkuil <hverkuil@xs4all.nl>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

diff --git a/drivers/media/i2c/ccs-pll.c b/drivers/media/i2c/ccs-pll.c
index 98ffbdf565f30f8a050a97eb5fbbc7c4733c0e75..fce3f0f18574a3031ad3b9627cbb344614563b8d 100644 (file)
--- a/drivers/media/i2c/ccs-pll.c
+++ b/drivers/media/i2c/ccs-pll.c
@@ -794,7 +794,7 @@ int ccs_pll_calculate(struct device *dev, const struct ccs_pll_limits *lim,
                op_lim_fr->min_pre_pll_clk_div, op_lim_fr->max_pre_pll_clk_div);
        max_op_pre_pll_clk_div =
                min_t(u16, op_lim_fr->max_pre_pll_clk_div,
-                     clk_div_even(pll->ext_clk_freq_hz /
+                     DIV_ROUND_UP(pll->ext_clk_freq_hz,
                                   op_lim_fr->min_pll_ip_clk_freq_hz));
        min_op_pre_pll_clk_div =
                max_t(u16, op_lim_fr->min_pre_pll_clk_div,