}
/* Handle misc other ops. */
+ if (e->Iex.Binop.op == Iop_8HLto16) {
+ HReg hi8 = newVRegI(env);
+ HReg lo8 = newVRegI(env);
+ HReg hi8s = iselIntExpr_R(env, e->Iex.Binop.arg1);
+ HReg lo8s = iselIntExpr_R(env, e->Iex.Binop.arg2);
+ addInstr(env, mk_MOVsd_RR(hi8s, hi8));
+ addInstr(env, mk_MOVsd_RR(lo8s, lo8));
+ addInstr(env, X86Instr_Sh32(Xsh_SHL, 8, X86RM_Reg(hi8)));
+ addInstr(env, X86Instr_Alu32R(Xalu_AND, X86RMI_Imm(0xFF), lo8));
+ addInstr(env, X86Instr_Alu32R(Xalu_OR, X86RMI_Reg(lo8), hi8));
+ return hi8;
+ }
+
if (e->Iex.Binop.op == Iop_16HLto32) {
HReg hi16 = newVRegI(env);
HReg lo16 = newVRegI(env);
addInstr(env, X86Instr_Set32(cond,dst));
return dst;
}
+ case Iop_1Sto8:
case Iop_1Sto16:
case Iop_1Sto32: {
/* could do better than this, but for now ... */
case Iop_32to1: vex_printf("32to1"); return;
case Iop_1Uto8: vex_printf("1Uto8"); return;
case Iop_1Uto32: vex_printf("1Uto32"); return;
+ case Iop_1Sto8: vex_printf("1Sto8"); return;
case Iop_1Sto16: vex_printf("1Sto16"); return;
case Iop_1Sto32: vex_printf("1Sto32"); return;
case Iop_1Sto64: vex_printf("1Sto64"); return;
case Iop_Or1: BINARY(Ity_Bit,Ity_Bit,Ity_Bit);
case Iop_Not1: UNARY(Ity_Bit,Ity_Bit);
case Iop_1Uto8: UNARY(Ity_I8,Ity_Bit);
+ case Iop_1Sto8: UNARY(Ity_I8,Ity_Bit);
case Iop_1Sto16: UNARY(Ity_I16,Ity_Bit);
case Iop_1Uto32: case Iop_1Sto32: UNARY(Ity_I32,Ity_Bit);
case Iop_1Sto64: UNARY(Ity_I64,Ity_Bit);
Iop_32to1, /* :: Ity_I32 -> Ity_Bit, just select bit[0] */
Iop_1Uto8, /* :: Ity_Bit -> Ity_I8, unsigned widen */
Iop_1Uto32, /* :: Ity_Bit -> Ity_I32, unsigned widen */
+ Iop_1Sto8, /* :: Ity_Bit -> Ity_I8, signed widen */
Iop_1Sto16, /* :: Ity_Bit -> Ity_I16, signed widen */
Iop_1Sto32, /* :: Ity_Bit -> Ity_I32, signed widen */
Iop_1Sto64, /* :: Ity_Bit -> Ity_I64, signed widen */