arm64: dts: renesas: r9a07g054: Add max-frequency to SDHI nodes

Add the max-frequency property set to 133333333 Hz (133.33 MHz) to both
SDHI0 and SDHI1 MMC controller nodes in the RZ/V2L (r9a07g054) device
tree, increasing performance by ca. 33%.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://patch.msgid.link/20260520115144.60067-4-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

diff --git a/arch/arm64/boot/dts/renesas/r9a07g054.dtsi b/arch/arm64/boot/dts/renesas/r9a07g054.dtsi
index 587fab0ceb3fa7e695d643d242c4ba80f7ef7ecc..f689996b58085e0b380015c17070743a53fc598c 100644 (file)
--- a/arch/arm64/boot/dts/renesas/r9a07g054.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a07g054.dtsi
@@ -1182,6 +1182,7 @@
                                 <&cpg CPG_MOD R9A07G054_SDHI0_IMCLK2>,
                                 <&cpg CPG_MOD R9A07G054_SDHI0_ACLK>;
                        clock-names = "core", "clkh", "cd", "aclk";
+                       max-frequency = <133333333>;
                        resets = <&cpg R9A07G054_SDHI0_IXRST>;
                        power-domains = <&cpg>;
                        status = "disabled";
@@ -1198,6 +1199,7 @@
                                 <&cpg CPG_MOD R9A07G054_SDHI1_IMCLK2>,
                                 <&cpg CPG_MOD R9A07G054_SDHI1_ACLK>;
                        clock-names = "core", "clkh", "cd", "aclk";
+                       max-frequency = <133333333>;
                        resets = <&cpg R9A07G054_SDHI1_IXRST>;
                        power-domains = <&cpg>;
                        status = "disabled";