{
int flags = opts->x_target_flags;
- /* iWMMXt and NEON are incompatible. */
- if (TARGET_IWMMXT
- && bitmap_bit_p (arm_active_target.isa, isa_bit_neon))
- error ("iWMMXt and NEON are incompatible");
-
/* Make sure that the processor choice does not conflict with any of the
other command line choices. */
if (TARGET_ARM_P (flags)
warning (0, "%<-g%> with %<-mno-apcs-frame%> may not give sensible "
"debugging");
- /* iWMMXt unsupported under Thumb mode. */
- if (TARGET_THUMB_P (flags) && TARGET_IWMMXT)
- error ("iWMMXt unsupported under Thumb mode");
-
if (TARGET_HARD_TP && TARGET_THUMB1_P (flags))
error ("cannot use %<-mtp=cp15%> with 16-bit Thumb");
if (arm_arch5t)
target_flags &= ~MASK_INTERWORK;
- if (TARGET_IWMMXT && !ARM_DOUBLEWORD_ALIGN)
- error ("iwmmxt requires an AAPCS compatible ABI for proper operation");
-
/* BPABI targets use linker tricks to allow interworking on cores
without thumb support. */
if (TARGET_INTERWORK
if (reg_needs_saving_p (regno))
return 0;
- if (TARGET_REALLY_IWMMXT)
- for (regno = FIRST_IWMMXT_REGNUM; regno <= LAST_IWMMXT_REGNUM; regno++)
- if (reg_needs_saving_p (regno))
- return 0;
-
return 1;
}
named_count avoids having to change the way arm handles 'named' */
pcum->named_count = 0;
pcum->nargs = 0;
-
- if (TARGET_REALLY_IWMMXT && fntype)
- {
- tree fn_arg;
-
- for (fn_arg = TYPE_ARG_TYPES (fntype);
- fn_arg;
- fn_arg = TREE_CHAIN (fn_arg))
- pcum->named_count += 1;
-
- if (! pcum->named_count)
- pcum->named_count = INT_MAX;
- }
}
/* Return 2 if double word alignment is required for argument passing,
&& INTVAL (index) > -1024
&& (INTVAL (index) & 3) == 0);
- if (TARGET_REALLY_IWMMXT && VALID_IWMMXT_REG_MODE (mode))
- return (code == CONST_INT
- && INTVAL (index) < 1024
- && INTVAL (index) > -1024
- && (INTVAL (index) & 3) == 0);
-
if (GET_MODE_SIZE (mode) <= 4
&& ! (arm_arch4
&& (mode == HImode
&& INTVAL (index) > -256
&& (INTVAL (index) & 3) == 0);
- if (TARGET_REALLY_IWMMXT && VALID_IWMMXT_REG_MODE (mode))
- {
- /* For DImode assume values will usually live in core regs
- and only allow LDRD addressing modes. */
- if (!TARGET_LDRD || mode != DImode)
- return (code == CONST_INT
- && INTVAL (index) < 1024
- && INTVAL (index) > -1024
- && (INTVAL (index) & 3) == 0);
- }
-
/* For quad modes, we restrict the constant offset to be slightly less
than what the instruction format permits. We do this because for
quad mode moves, we will actually decompose them into two separate
if (cfun->machine->lr_save_eliminated)
save_reg_mask &= ~ (1 << LR_REGNUM);
- if (TARGET_REALLY_IWMMXT
- && ((bit_count (save_reg_mask)
- + ARM_NUM_INTS (crtl->args.pretend_args_size +
- arm_compute_static_chain_stack_bytes())
- ) % 2) != 0)
- {
- /* The total number of registers that are going to be pushed
- onto the stack is odd. We need to ensure that the stack
- is 64-bit aligned before we start to save iWMMXt registers,
- and also before we start to create locals. (A local variable
- might be a double or long long which we will load/store using
- an iWMMXt instruction). Therefore we need to push another
- ARM register, so that the stack will be 64-bit aligned. We
- try to avoid using the arg registers (r0 -r3) as they might be
- used to pass values in a tail call. */
- for (reg = 4; reg <= 12; reg++)
- if ((save_reg_mask & (1 << reg)) == 0)
- break;
-
- if (reg <= 12)
- save_reg_mask |= (1 << reg);
- else
- {
- cfun->machine->sibcall_blocked = 1;
- save_reg_mask |= (1 << 3);
- }
- }
-
/* We may need to push an additional register for use initializing the
PIC base register. */
if (TARGET_THUMB2 && IS_NESTED (func_type) && flag_pic
live_regs_mask |= (1 << SP_REGNUM);
}
else
- gcc_assert (IS_INTERRUPT (func_type) || TARGET_REALLY_IWMMXT);
+ gcc_assert (IS_INTERRUPT (func_type));
}
/* On some ARM architectures it is faster to use LDR rather than
if (TARGET_32BIT)
{
- unsigned int regno;
-
offsets->saved_regs_mask = arm_compute_save_core_reg_mask ();
core_saved = bit_count (offsets->saved_regs_mask) * 4;
saved = core_saved;
preserve that condition at any subroutine call. We also require the
soft frame pointer to be doubleword aligned. */
- if (TARGET_REALLY_IWMMXT)
- {
- /* Check for the call-saved iWMMXt registers. */
- for (regno = FIRST_IWMMXT_REGNUM;
- regno <= LAST_IWMMXT_REGNUM;
- regno++)
- if (reg_needs_saving_p (regno))
- saved += 8;
- }
-
func_type = arm_current_func_type ();
/* Space for saved VFP registers. */
if (! IS_VOLATILE (func_type)
int saved_size = 0;
unsigned reg;
unsigned start_reg;
- rtx insn;
-
- if (TARGET_REALLY_IWMMXT)
- for (reg = LAST_IWMMXT_REGNUM; reg >= FIRST_IWMMXT_REGNUM; reg--)
- if (reg_needs_saving_p (reg))
- {
- insn = gen_rtx_PRE_DEC (Pmode, stack_pointer_rtx);
- insn = gen_rtx_MEM (V2SImode, insn);
- insn = emit_set_insn (insn, gen_rtx_REG (V2SImode, reg));
- RTX_FRAME_RELATED_P (insn) = 1;
- saved_size += 8;
- }
if (TARGET_VFP_BASE)
{
return false;
}
- if (TARGET_REALLY_IWMMXT)
- {
- if (IS_IWMMXT_GR_REGNUM (regno))
- return mode == SImode;
-
- if (IS_IWMMXT_REGNUM (regno))
- return VALID_IWMMXT_REG_MODE (mode);
- }
-
/* We allow almost any value to be stored in the general registers.
Restrict doubleword quantities to even register pairs in ARM state
so that we can use ldrd. The same restriction applies for MVE
gen_rtx_REG (SImode, IP_REGNUM));
}
- if (TARGET_IWMMXT)
- {
- /* The frame pointer is guaranteed to be non-double-word aligned, as
- it is set to double-word-aligned old_stack_pointer - 4. */
- rtx_insn *insn;
- int lrm_count = (num_regs % 2) ? (num_regs + 2) : (num_regs + 1);
-
- for (i = LAST_IWMMXT_REGNUM; i >= FIRST_IWMMXT_REGNUM; i--)
- if (reg_needs_saving_p (i))
- {
- rtx addr = gen_frame_mem (V2SImode,
- plus_constant (Pmode, hard_frame_pointer_rtx,
- - lrm_count * 4));
- insn = emit_insn (gen_movsi (gen_rtx_REG (V2SImode, i), addr));
- REG_NOTES (insn) = alloc_reg_note (REG_CFA_RESTORE,
- gen_rtx_REG (V2SImode, i),
- NULL_RTX);
- lrm_count += 2;
- }
- }
-
/* saved_regs_mask should contain IP which contains old stack pointer
at the time of activation creation. Since SP and IP are adjacent registers,
we can restore the value directly into SP. */
stack_pointer_rtx);
}
- if (TARGET_IWMMXT)
- for (i = FIRST_IWMMXT_REGNUM; i <= LAST_IWMMXT_REGNUM; i++)
- if (reg_needs_saving_p (i))
- {
- rtx_insn *insn;
- rtx addr = gen_rtx_MEM (V2SImode,
- gen_rtx_POST_INC (SImode,
- stack_pointer_rtx));
- set_mem_alias_set (addr, get_frame_alias_set ());
- insn = emit_insn (gen_movsi (gen_rtx_REG (V2SImode, i), addr));
- REG_NOTES (insn) = alloc_reg_note (REG_CFA_RESTORE,
- gen_rtx_REG (V2SImode, i),
- NULL_RTX);
- arm_add_cfa_adjust_cfa_note (insn, UNITS_PER_WORD,
- stack_pointer_rtx, stack_pointer_rtx);
- }
-
if (saved_regs_mask)
{
rtx insn;
|| mode == V8BFmode))
return true;
- if ((TARGET_NEON || TARGET_IWMMXT)
+ if (TARGET_NEON
&& ((mode == V2SImode)
|| (mode == V4HImode)
|| (mode == V8QImode)))
default:;
}
- if (TARGET_REALLY_IWMMXT)
- switch (mode)
- {
- case E_SImode:
- return V2SImode;
- case E_HImode:
- return V4HImode;
- case E_QImode:
- return V8QImode;
-
- default:;
- }
-
if (TARGET_HAVE_MVE)
switch (mode)
{
fixed_regs[VPR_REGNUM] = 0;
}
- if (TARGET_REALLY_IWMMXT && !TARGET_GENERAL_REGS_ONLY)
- {
- regno = FIRST_IWMMXT_GR_REGNUM;
- /* The 2002/10/09 revision of the XScale ABI has wCG0
- and wCG1 as call-preserved registers. The 2002/11/21
- revision changed this so that all wCG registers are
- scratch registers. */
- for (regno = FIRST_IWMMXT_GR_REGNUM;
- regno <= LAST_IWMMXT_GR_REGNUM; ++ regno)
- fixed_regs[regno] = 0;
- /* The XScale ABI has wR0 - wR9 as scratch registers,
- the rest as call-preserved registers. */
- for (regno = FIRST_IWMMXT_REGNUM;
- regno <= LAST_IWMMXT_REGNUM; ++ regno)
- {
- fixed_regs[regno] = 0;
- call_used_regs[regno] = regno < FIRST_IWMMXT_REGNUM + 10;
- }
- }
-
if ((unsigned) PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM)
{
fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1;
projects / thirdparty / gcc.git / commitdiff
