With -fpu=neon DI mode shifts are expanded after reload.

With -fpu=neon DI mode shifts are expanded after reload.  DI mode registers can
either fully or partially overlap on both ARM and Thumb-2.  However the shift
expansion code can only deal with the full overlap case, and generates incorrect
code for partial overlaps.  The fix is to add new variants that support either
full overlap or no overlap.

	Backport from mainline
    gcc/
	PR target/78041
	* config/arm/neon.md (ashldi3_neon): Add "r 0 i" and "&r r i" variants.
	Remove partial overlap check for shift by 1.
	(ashldi3_neon): Likewise.
    testsuite/
	* gcc.target/arm/pr78041.c: New test.

From-SVN: r244872

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index c6875f40bf90420b03c1507122fb4e8c369fedda..b241a85663e2e420ea2598565957a6e69b6f77ed 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,11 @@
+2017-01-24  Wilco Dijkstra  <wdijkstr@arm.com>
+
+       Backport from mainline
+       PR target/78041
+       * config/arm/neon.md (ashldi3_neon): Add "r 0 i" and "&r r i" variants.
+       Remove partial overlap check for shift by 1.
+       (ashldi3_neon): Likewise.
+
 2017-01-24  Richard Biener  <rguenther@suse.de>
 
        Backport from mainline

diff --git a/gcc/config/arm/neon.md b/gcc/config/arm/neon.md
index 63c327ec68cacc85446c2c4aa3bf99eee9ebe074..a05302720c333ba8c99240bf6afaae2d872c1c65 100644 (file)
--- a/gcc/config/arm/neon.md
+++ b/gcc/config/arm/neon.md
@@ -1015,12 +1015,12 @@
 )
 
 (define_insn_and_split "ashldi3_neon"
-  [(set (match_operand:DI 0 "s_register_operand"           "= w, w,?&r,?r, ?w,w")
-       (ashift:DI (match_operand:DI 1 "s_register_operand" " 0w, w, 0r, r, 0w,w")
-                  (match_operand:SI 2 "general_operand"    "rUm, i,  r, i,rUm,i")))
-   (clobber (match_scratch:SI 3                                    "= X, X,?&r, X,  X,X"))
-   (clobber (match_scratch:SI 4                                    "= X, X,?&r, X,  X,X"))
-   (clobber (match_scratch:DI 5                                    "=&w, X,  X, X, &w,X"))
+  [(set (match_operand:DI 0 "s_register_operand"           "= w, w,?&r,?r,?&r, ?w,w")
+       (ashift:DI (match_operand:DI 1 "s_register_operand" " 0w, w, 0r, 0,  r, 0w,w")
+                  (match_operand:SI 2 "general_operand"    "rUm, i,  r, i,  i,rUm,i")))
+   (clobber (match_scratch:SI 3                                    "= X, X,?&r, X,  X,  X,X"))
+   (clobber (match_scratch:SI 4                                    "= X, X,?&r, X,  X,  X,X"))
+   (clobber (match_scratch:DI 5                                    "=&w, X,  X, X,  X, &w,X"))
    (clobber (reg:CC_C CC_REGNUM))]
   "TARGET_NEON"
   "#"
@@ -1052,9 +1052,11 @@
       }
     else
       {
-       if (CONST_INT_P (operands[2]) && INTVAL (operands[2]) == 1
-           && (!reg_overlap_mentioned_p (operands[0], operands[1])
-               || REGNO (operands[0]) == REGNO (operands[1])))
+       /* The shift expanders support either full overlap or no overlap.  */
+       gcc_assert (!reg_overlap_mentioned_p (operands[0], operands[1])
+                   || REGNO (operands[0]) == REGNO (operands[1]));
+
+       if (operands[2] == CONST1_RTX (SImode))
          /* This clobbers CC.  */
          emit_insn (gen_arm_ashldi3_1bit (operands[0], operands[1]));
        else
@@ -1063,8 +1065,8 @@
       }
     DONE;
   }"
-  [(set_attr "arch" "neon_for_64bits,neon_for_64bits,*,*,avoid_neon_for_64bits,avoid_neon_for_64bits")
-   (set_attr "opt" "*,*,speed,speed,*,*")
+  [(set_attr "arch" "neon_for_64bits,neon_for_64bits,*,*,*,avoid_neon_for_64bits,avoid_neon_for_64bits")
+   (set_attr "opt" "*,*,speed,speed,speed,*,*")
    (set_attr "type" "multiple")]
 )
 
@@ -1113,12 +1115,12 @@
 ;; ashrdi3_neon
 ;; lshrdi3_neon
 (define_insn_and_split "<shift>di3_neon"
-  [(set (match_operand:DI 0 "s_register_operand"            "= w, w,?&r,?r,?w,?w")
-       (rshifts:DI (match_operand:DI 1 "s_register_operand" " 0w, w, 0r, r,0w, w")
-                   (match_operand:SI 2 "reg_or_int_operand" "  r, i,  r, i, r, i")))
-   (clobber (match_scratch:SI 3                                     "=2r, X, &r, X,2r, X"))
-   (clobber (match_scratch:SI 4                                     "= X, X, &r, X, X, X"))
-   (clobber (match_scratch:DI 5                                     "=&w, X,  X, X,&w, X"))
+  [(set (match_operand:DI 0 "s_register_operand"            "= w, w,?&r,?r,?&r,?w,?w")
+       (rshifts:DI (match_operand:DI 1 "s_register_operand" " 0w, w, 0r, 0,  r,0w, w")
+                   (match_operand:SI 2 "reg_or_int_operand" "  r, i,  r, i,  i, r, i")))
+   (clobber (match_scratch:SI 3                                     "=2r, X, &r, X,  X,2r, X"))
+   (clobber (match_scratch:SI 4                                     "= X, X, &r, X,  X, X, X"))
+   (clobber (match_scratch:DI 5                                     "=&w, X,  X, X, X,&w, X"))
    (clobber (reg:CC CC_REGNUM))]
   "TARGET_NEON"
   "#"
@@ -1154,9 +1156,11 @@
       }
     else
       {
-       if (CONST_INT_P (operands[2]) && INTVAL (operands[2]) == 1
-           && (!reg_overlap_mentioned_p (operands[0], operands[1])
-               || REGNO (operands[0]) == REGNO (operands[1])))
+       /* The shift expanders support either full overlap or no overlap.  */
+       gcc_assert (!reg_overlap_mentioned_p (operands[0], operands[1])
+                   || REGNO (operands[0]) == REGNO (operands[1]));
+
+       if (operands[2] == CONST1_RTX (SImode))
          /* This clobbers CC.  */
          emit_insn (gen_arm_<shift>di3_1bit (operands[0], operands[1]));
        else
@@ -1167,8 +1171,8 @@
 
     DONE;
   }"
-  [(set_attr "arch" "neon_for_64bits,neon_for_64bits,*,*,avoid_neon_for_64bits,avoid_neon_for_64bits")
-   (set_attr "opt" "*,*,speed,speed,*,*")
+  [(set_attr "arch" "neon_for_64bits,neon_for_64bits,*,*,*,avoid_neon_for_64bits,avoid_neon_for_64bits")
+   (set_attr "opt" "*,*,speed,speed,speed,*,*")
    (set_attr "type" "multiple")]
 )
 

diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index 6b1b2983358dc34d0f729b6f7f677bc2ee27b233..f20224e4e252cca5200d28be93480ef3dadb1595 100644 (file)
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,9 @@
+2017-01-24  Wilco Dijkstra  <wdijkstr@arm.com>
+
+       Backport from mainline
+       PR target/78041
+       * gcc.target/arm/pr78041.c: New test.
+
 2017-01-24  Richard Biener  <rguenther@suse.de>
 
        Backport from mainline