Merge branch 'pci/controller/link_train_delay'

- Add pci_host_common_link_train_delay() for the mandatory delay after
  > 5GT/s Link training completes and use it for cadence HPA, j721e, LGA;
  dwc; aardvark, mediatek-gen3, rzg3s (Hans Zhang)

* pci/controller/link_train_delay:
  PCI: rzg3s-host: Use common pci_host_common_link_train_delay() helper
  PCI: mediatek-gen3: Add 100 ms delay after link up
  PCI: aardvark: Add 100 ms delay after link training
  PCI: dwc: Use common pci_host_common_link_train_delay() helper
  PCI: cadence-hpa: Add post-link delay
  PCI: cadence: Add post-link delay for LGA and j721e glue driver
  PCI: Add pci_host_common_link_train_delay() helper

# Conflicts:
#	drivers/pci/controller/pci-host-common.h

diff --cc drivers/pci/controller/dwc/pcie-designware.c
Simple merge

diff --cc drivers/pci/controller/pci-host-common.h
index 458678051d27f0ccde19911ed9d73157190c85d0,d709f7e3e11a3c4bbadbad97bef014620c7f3568..9f0f36a322214885f11a9b7ac91c83b2b42fcb00
--- 1/drivers/pci/controller/pci-host-common.h
--- 2/drivers/pci/controller/pci-host-common.h
+++ b/drivers/pci/controller/pci-host-common.h
@@@ -10,36 -10,11 +10,39 @@@
  #ifndef _PCI_HOST_COMMON_H
  #define _PCI_HOST_COMMON_H
  
+ #include <linux/delay.h>
+ #include "../pci.h"
+ 
  struct pci_ecam_ops;
  
 +/**
 + * struct pci_host_perst - PERST# GPIO descriptor
 + * @list: List node for linking multiple PERST# GPIOs
 + * @desc: GPIO descriptor for PERST# signal
 + *
 + * This structure holds a single PERST# GPIO descriptor.
 + */
 +struct pci_host_perst {
 +      struct list_head        list;
 +      struct gpio_desc        *desc;
 +};
 +
 +/**
 + * struct pci_host_port - Generic Root Port properties
 + * @list: List node for linking multiple ports
 + * @perst: List of PERST# GPIO descriptors for this port and its children
 + *
 + * This structure contains common properties that can be parsed from
 + * Root Port device tree nodes.
 + */
 +struct pci_host_port {
 +      struct list_head        list;
 +      struct list_head        perst;
 +};
 +
 +void pci_host_common_delete_ports(void *data);
 +int pci_host_common_parse_ports(struct device *dev,
 +                              struct pci_host_bridge *bridge);
  int pci_host_common_probe(struct platform_device *pdev);
  int pci_host_common_init(struct platform_device *pdev,
                         struct pci_host_bridge *bridge,
@@@ -49,6 -24,17 +52,20 @@@ void pci_host_common_remove(struct plat
  struct pci_config_window *pci_host_common_ecam_create(struct device *dev,
        struct pci_host_bridge *bridge, const struct pci_ecam_ops *ops);
  
 +bool pci_host_common_d3cold_possible(struct pci_host_bridge *bridge,
 +                                   bool *pme_capable);
++
+ /**
+  * pci_host_common_link_train_delay - Wait 100 ms if link speed > 5 GT/s
+  * @max_link_speed: the maximum link speed (2 = 5.0 GT/s, 3 = 8.0 GT/s, ...)
+  *
+  * Must be called after Link training completes and before the first
+  * Configuration Request is sent.
+  */
+ static inline void pci_host_common_link_train_delay(int max_link_speed)
+ {
+       if (max_link_speed > 2)
+               msleep(PCIE_RESET_CONFIG_WAIT_MS);
+ }
+ 
  #endif

diff --cc drivers/pci/controller/pcie-mediatek-gen3.c
Simple merge