Add -mtune-ctrl=sse_typeless_stores to avx256-unaligned-store-2.c

Since avx256-unaligned-store-2.c scans typeless SSE stores, add
-mtune-ctrl=sse_typeless_stores to enable typeless SSE stores.

	* gcc.target/i386/avx256-unaligned-store-2.c: Add
	-mtune-ctrl=sse_typeless_stores.

From-SVN: r235296

diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index a9dc717b29456ece776f6b4b34bfbda01e5433d4..1bb941147ce855159683bf56c5a3d8822b1a3bc4 100644 (file)
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,8 @@
+2016-04-20  H.J. Lu  <hongjiu.lu@intel.com>
+
+       * gcc.target/i386/avx256-unaligned-store-2.c: Add
+       -mtune-ctrl=sse_typeless_stores.
+
 2016-04-20  H.J. Lu  <hongjiu.lu@intel.com>
 
        * gcc.target/i386/avx256-unaligned-load-1.c: Update load scan.

diff --git a/gcc/testsuite/gcc.target/i386/avx256-unaligned-store-2.c b/gcc/testsuite/gcc.target/i386/avx256-unaligned-store-2.c
index 817be172b98b6fee3dbf40e79a69fd589ace9eb4..87285c680d373100294a6f139899d311f8b2c553 100644 (file)
--- a/gcc/testsuite/gcc.target/i386/avx256-unaligned-store-2.c
+++ b/gcc/testsuite/gcc.target/i386/avx256-unaligned-store-2.c
@@ -1,5 +1,5 @@
 /* { dg-do compile { target { ! ia32 } } } */
-/* { dg-options "-O3 -dp -mavx -mavx256-split-unaligned-store -mno-prefer-avx128" } */
+/* { dg-options "-O3 -mtune-ctrl=sse_typeless_stores -dp -mavx -mavx256-split-unaligned-store -mno-prefer-avx128" } */
 
 #define N 1024