net/mlx5: Add sd_group_size bits for SD management

Currently, mlx5 is querying the MPIR register to get the number of PFs
that should comprise the SD group.
However, this register does not reflect the correct number in complex
deployments. Hence, add an sd_group_size field to nic_vport_context to
determine the correct number of PFs, and add an sd_group_size capability
bit to indicate whether FW supports it.

Signed-off-by: Shay Drory <shayd@nvidia.com>
Reviewed-by: Moshe Shemesh <moshe@nvidia.com>
Signed-off-by: Tariq Toukan <tariqt@nvidia.com>
Link: https://patch.msgid.link/20260529052359.389413-3-tariqt@nvidia.com
Signed-off-by: Leon Romanovsky <leon@kernel.org>

diff --git a/include/linux/mlx5/mlx5_ifc.h b/include/linux/mlx5/mlx5_ifc.h
index d23332cdd9b3f95bf4e16846fada98926238c512..4f59b7e8a3d5d64a912575bba85e60e040959bcb 100644 (file)
--- a/include/linux/mlx5/mlx5_ifc.h
+++ b/include/linux/mlx5/mlx5_ifc.h
@@ -1986,7 +1986,8 @@ struct mlx5_ifc_cmd_hca_cap_bits {
        u8         basic_cyclic_rcv_wqe[0x1];
        u8         reserved_at_381[0x2];
        u8         log_max_rmp[0x5];
-       u8         reserved_at_388[0x3];
+       u8         sd_group_size[0x1];
+       u8         reserved_at_389[0x2];
        u8         log_max_rqt[0x5];
        u8         reserved_at_390[0x3];
        u8         log_max_rqt_size[0x5];
@@ -4469,7 +4470,9 @@ struct mlx5_ifc_nic_vport_context_bits {
 
        u8         reserved_at_100[0x1];
        u8         sd_group[0x3];
-       u8         reserved_at_104[0x1c];
+       u8         reserved_at_104[0x4];
+       u8         sd_group_size[0x8];
+       u8         reserved_at_110[0x10];
 
        u8         reserved_at_120[0x10];
        u8         mtu[0x10];