[ARM][PR82989] Fix unexpected use of NEON instructions for shifts

This is a backport of r258677 and r258723 of trunk.

*** gcc/ChangeLog ***

2018-03-27  Sudakshina Das  <sudi.das@arm.com>

	Backport from mainline:
	2018-03-20  Sudakshina Das  <sudi.das@arm.com>

	PR target/82989
	* config/arm/neon.md (ashldi3_neon): Update ?s for constraints
	to favor GPR over NEON registers.
	(<shift>di3_neon): Likewise.

*** gcc/testsuite/ChangeLog ***

2018-03-27  Sudakshina Das  <sudi.das@arm.com>

	Backport from mainline:
	2018-03-20  Sudakshina Das  <sudi.das@arm.com>

	PR target/82989
	* gcc.target/arm/pr82989.c: New test.

	Backport from mainline:
	2018-03-21  Sudakshina Das  <sudi.das@arm.com>

	PR target/82989
	* gcc.target/arm/pr82989.c: Change dg scan-assembly directives.

From-SVN: r258884

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index f02d5695499e211251397a3577a6aa82a0c7e3a5..0cbc803270e9e7ab585a11a8ab3e600adc355e35 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,13 @@
+2018-03-27  Sudakshina Das  <sudi.das@arm.com>
+
+       Backport from mainline:
+       2018-03-20  Sudakshina Das  <sudi.das@arm.com>
+
+       PR target/82989
+       * config/arm/neon.md (ashldi3_neon): Update ?s for constraints
+       to favor GPR over NEON registers.
+       (<shift>di3_neon): Likewise.
+
 2018-03-27  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
 
        Backport from mainline

diff --git a/gcc/config/arm/neon.md b/gcc/config/arm/neon.md
index 1d51c4045a1779fbd7927c94cdd6752b95cdabc7..ac46b0418bd1a3dae3a0077385e6d9b1d16b519c 100644 (file)
--- a/gcc/config/arm/neon.md
+++ b/gcc/config/arm/neon.md
@@ -1045,12 +1045,12 @@
 )
 
 (define_insn_and_split "ashldi3_neon"
-  [(set (match_operand:DI 0 "s_register_operand"           "= w, w,?&r,?r,?&r, ?w,w")
-       (ashift:DI (match_operand:DI 1 "s_register_operand" " 0w, w, 0r, 0,  r, 0w,w")
-                  (match_operand:SI 2 "general_operand"    "rUm, i,  r, i,  i,rUm,i")))
-   (clobber (match_scratch:SI 3                                    "= X, X,?&r, X,  X,  X,X"))
-   (clobber (match_scratch:SI 4                                    "= X, X,?&r, X,  X,  X,X"))
-   (clobber (match_scratch:DI 5                                    "=&w, X,  X, X,  X, &w,X"))
+  [(set (match_operand:DI 0 "s_register_operand"           "= w, w, &r, r, &r, ?w,?w")
+       (ashift:DI (match_operand:DI 1 "s_register_operand" " 0w, w, 0r, 0,  r, 0w, w")
+                  (match_operand:SI 2 "general_operand"    "rUm, i,  r, i,  i,rUm, i")))
+   (clobber (match_scratch:SI 3                                    "= X, X, &r, X,  X,  X, X"))
+   (clobber (match_scratch:SI 4                                    "= X, X, &r, X,  X,  X, X"))
+   (clobber (match_scratch:DI 5                                    "=&w, X,  X, X,  X, &w, X"))
    (clobber (reg:CC_C CC_REGNUM))]
   "TARGET_NEON"
   "#"
@@ -1145,7 +1145,7 @@
 ;; ashrdi3_neon
 ;; lshrdi3_neon
 (define_insn_and_split "<shift>di3_neon"
-  [(set (match_operand:DI 0 "s_register_operand"            "= w, w,?&r,?r,?&r,?w,?w")
+  [(set (match_operand:DI 0 "s_register_operand"            "= w, w, &r, r, &r,?w,?w")
        (RSHIFTS:DI (match_operand:DI 1 "s_register_operand" " 0w, w, 0r, 0,  r,0w, w")
                    (match_operand:SI 2 "reg_or_int_operand" "  r, i,  r, i,  i, r, i")))
    (clobber (match_scratch:SI 3                                     "=2r, X, &r, X,  X,2r, X"))

diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index 9f745cf9e4dec753734ff457d9d948f21952d3f1..e958e2841c4afd9bb88737b778eab793f50c7105 100644 (file)
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,17 @@
+2018-03-27  Sudakshina Das  <sudi.das@arm.com>
+
+       Backport from mainline:
+       2018-03-20  Sudakshina Das  <sudi.das@arm.com>
+
+       PR target/82989
+       * gcc.target/arm/pr82989.c: New test.
+
+       Backport from mainline:
+       2018-03-21  Sudakshina Das  <sudi.das@arm.com>
+
+       PR target/82989
+       * gcc.target/arm/pr82989.c: Change dg scan-assembly directives.
+
 2018-03-27  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
 
        Backport from mainline

diff --git a/gcc/testsuite/gcc.target/arm/pr82989.c b/gcc/testsuite/gcc.target/arm/pr82989.c
new file mode 100644 (file)
index 0000000..8519c3f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/pr82989.c
@@ -0,0 +1,33 @@
+/* PR target/82989.  */
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-skip-if "avoid conflicts with multilib options" { *-*-* } { "-mcpu=*" } { "-mcpu=cortex-a8" } } */
+/* { dg-skip-if "avoid conflicts with multilib options" { *-*-* } { "-mfpu=*" } { "-mfpu=neon" } } */
+/* { dg-skip-if "avoid conflicts with multilib options" { *-*-* } { "-mfloat-abi=*" } { "-mfloat-abi=hard" } } */
+/* { dg-options "-O2 -mcpu=cortex-a8 -mfpu=neon -mfloat-abi=hard" } */
+/* { dg-add-options arm_neon } */
+
+typedef unsigned long long uint64_t;
+
+void f_shr_imm (uint64_t *a)
+{
+  *a += *a >> 32;
+}
+
+void f_shr_reg (uint64_t *a, uint64_t b)
+{
+  *a += *a >> b;
+}
+
+void f_shl_imm (uint64_t *a)
+{
+  *a += *a << 32;
+}
+
+void f_shl_reg (uint64_t *a, uint64_t b)
+{
+  *a += *a << b;
+}
+/* { dg-final { scan-assembler-not "vshl*" } } */
+/* { dg-final { scan-assembler-not "vshr*" } } */
+/* { dg-final { scan-assembler-not "vmov*" } } */