PCI: xilinx-nwl: Enable the clock through CCF

Enable PCIe reference clock. There is no remove function that's why
this should be enough for simple operation.
Normally this clock is enabled by default by firmware but there are
usecases where this clock should be enabled by driver itself.
It is also good that PCIe clock is recorded in a clock framework.

Link: https://lore.kernel.org/r/ee6997a08fab582b1c6de05f8be184f3fe8d5357.1624618100.git.michal.simek@xilinx.com
Fixes: ab597d35ef11 ("PCI: xilinx-nwl: Add support for Xilinx NWL PCIe Host Controller")
Signed-off-by: Hyun Kwon <hyun.kwon@xilinx.com>
Signed-off-by: Bharat Kumar Gogada <bharat.kumar.gogada@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Cc: stable@vger.kernel.org

diff --git a/drivers/pci/controller/pcie-xilinx-nwl.c b/drivers/pci/controller/pcie-xilinx-nwl.c
index 8689311c5ef66a75dd1b70ce769b769eea06e142..1c3d5b87ef20edbc1fc64f8472719d4825636753 100644 (file)
--- a/drivers/pci/controller/pcie-xilinx-nwl.c
+++ b/drivers/pci/controller/pcie-xilinx-nwl.c
@@ -6,6 +6,7 @@
  * (C) Copyright 2014 - 2015, Xilinx, Inc.
  */
 
+#include <linux/clk.h>
 #include <linux/delay.h>
 #include <linux/interrupt.h>
 #include <linux/irq.h>
@@ -169,6 +170,7 @@ struct nwl_pcie {
        u8 last_busno;
        struct nwl_msi msi;
        struct irq_domain *legacy_irq_domain;
+       struct clk *clk;
        raw_spinlock_t leg_mask_lock;
 };
 
@@ -823,6 +825,16 @@ static int nwl_pcie_probe(struct platform_device *pdev)
                return err;
        }
 
+       pcie->clk = devm_clk_get(dev, NULL);
+       if (IS_ERR(pcie->clk))
+               return PTR_ERR(pcie->clk);
+
+       err = clk_prepare_enable(pcie->clk);
+       if (err) {
+               dev_err(dev, "can't enable PCIe ref clock\n");
+               return err;
+       }
+
        err = nwl_pcie_bridge_init(pcie);
        if (err) {
                dev_err(dev, "HW Initialization failed\n");