clk: mediaTek: mt7986: add clock tree type flags

Add clock tree type flags to the mt7986 clock tree structures. These
will be used later for parent lookup.

Link: https://patch.msgid.link/20260710-mtk-clk-parent-lookup-improvements-v2-7-f3f3a4a28dca@baylibre.com
Signed-off-by: David Lechner <dlechner@baylibre.com>

diff --git a/drivers/clk/mediatek/clk-mt7986.c b/drivers/clk/mediatek/clk-mt7986.c
index 9c6514120a6d15cf4d0e4bade8819c0855d4429d..a5301fbe8cf439de1ead9857dd2af67fd05ea288 100644 (file)
--- a/drivers/clk/mediatek/clk-mt7986.c
+++ b/drivers/clk/mediatek/clk-mt7986.c
@@ -530,6 +530,7 @@ static const struct mtk_clk_tree mt7986_fixed_pll_clk_tree = {
        .fclks = fixed_pll_clks,
        .num_fclks = ARRAY_SIZE(fixed_pll_clks),
        .flags = CLK_PARENT_APMIXED,
+       .type = MTK_CLK_TREE_APMIXED,
 };
 
 static const struct mtk_clk_tree mt7986_topckgen_clk_tree = {
@@ -544,6 +545,7 @@ static const struct mtk_clk_tree mt7986_topckgen_clk_tree = {
        .num_fdivs = ARRAY_SIZE(top_fixed_divs),
        .num_muxes = ARRAY_SIZE(top_muxes),
        .flags = CLK_PARENT_TOPCKGEN,
+       .type = MTK_CLK_TREE_TOPCKGEN,
 };
 
 static const struct mtk_clk_tree mt7986_infracfg_clk_tree = {
@@ -559,6 +561,12 @@ static const struct mtk_clk_tree mt7986_infracfg_clk_tree = {
        .num_muxes = ARRAY_SIZE(infra_muxes),
        .num_gates = ARRAY_SIZE(infracfg_gates),
        .flags = CLK_PARENT_INFRASYS,
+       .type = MTK_CLK_TREE_INFRASYS,
+};
+
+static const struct mtk_clk_tree mt7986_clk_tree = {
+       .ext_clk_rates = ext_clock_rates,
+       .num_ext_clks = ARRAY_SIZE(ext_clock_rates),
 };
 
 static const struct udevice_id mt7986_fixed_pll_compat[] = {
@@ -591,6 +599,7 @@ U_BOOT_DRIVER(mtk_clk_apmixedsys) = {
        .name = "mt7986-clock-fixed-pll",
        .id = UCLASS_CLK,
        .of_match = mt7986_fixed_pll_compat,
+       .bind = mtk_common_clk_parent_bind,
        .probe = mt7986_fixed_pll_probe,
        .priv_auto = sizeof(struct mtk_clk_priv),
        .ops = &mtk_clk_fixed_pll_ops,
@@ -601,6 +610,7 @@ U_BOOT_DRIVER(mtk_clk_topckgen) = {
        .name = "mt7986-clock-topckgen",
        .id = UCLASS_CLK,
        .of_match = mt7986_topckgen_compat,
+       .bind = mtk_common_clk_parent_bind,
        .probe = mt7986_topckgen_probe,
        .priv_auto = sizeof(struct mtk_clk_priv),
        .ops = &mtk_clk_topckgen_ops,
@@ -621,6 +631,7 @@ U_BOOT_DRIVER(mtk_clk_infracfg) = {
        .name = "mt7986-clock-infracfg",
        .id = UCLASS_CLK,
        .of_match = mt7986_infracfg_compat,
+       .bind = mtk_common_clk_parent_bind,
        .probe = mt7986_infracfg_probe,
        .priv_auto = sizeof(struct mtk_clk_priv),
        .ops = &mtk_clk_infrasys_ops,
@@ -649,7 +660,7 @@ static const struct mtk_gate eth_cgs[] = {
 
 static int mt7986_ethsys_probe(struct udevice *dev)
 {
-       return mtk_common_clk_gate_init(dev, &mt7986_topckgen_clk_tree, eth_cgs,
+       return mtk_common_clk_gate_init(dev, &mt7986_clk_tree, eth_cgs,
                                        ARRAY_SIZE(eth_cgs), 0);
 }