[PATCH] RISC-V: Make the setCC/REE tests robust to instruction selection

These tests were checking that the output of the setCC instruction was bit
flipped, but it looks like they're really designed to test that
redundant sign extension elimination fires on conditionals from function
inputs.  Jeff just posed a patch to clean this code up with trips up on
the arbitrary xori/snez instruction selection decision changing, so
let's just robustify the tests.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/sge.c: Adjust regex to match the input.
	* gcc.target/riscv/sgeu.c: Likewise.
	* gcc.target/riscv/sle.c: Likewise.
	* gcc.target/riscv/sleu.c: Likewise.

diff --git a/gcc/testsuite/gcc.target/riscv/sge.c b/gcc/testsuite/gcc.target/riscv/sge.c
index 5f7e7ae82db0ebcdcd7d882fabc2e7907dd4fa28..70f934c4d0f143f9e754fdb6cdd4dffd7504f027 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/sge.c
+++ b/gcc/testsuite/gcc.target/riscv/sge.c
@@ -8,5 +8,5 @@ sge (int x, int y)
   return x >= y;
 }
 
-/* { dg-final { scan-assembler "\\sxori\\sa0,a0,1\n\\sret\n" } } */
+/* { dg-final { scan-assembler "slt\\sa0,a0,a1" } } */
 /* { dg-final { scan-assembler-not "andi|sext\\.w" } } */

diff --git a/gcc/testsuite/gcc.target/riscv/sgeu.c b/gcc/testsuite/gcc.target/riscv/sgeu.c
index 234b9aa52bd0b93924eaf5cc03ef01f024b9e10e..0ff21cfe5e019e09f88f504f6856b174cb4039ce 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/sgeu.c
+++ b/gcc/testsuite/gcc.target/riscv/sgeu.c
@@ -8,5 +8,5 @@ sgeu (unsigned int x, unsigned int y)
   return x >= y;
 }
 
-/* { dg-final { scan-assembler "\\sxori\\sa0,a0,1\n\\sret\n" } } */
+/* { dg-final { scan-assembler "sltu\\sa0,a0,a1" } } */
 /* { dg-final { scan-assembler-not "andi|sext\\.w" } } */

diff --git a/gcc/testsuite/gcc.target/riscv/sle.c b/gcc/testsuite/gcc.target/riscv/sle.c
index 3259c19159880cd9b350f2bcbae8a301409f3cf0..770840d0564f5ead719fe22b11c358b76524c03d 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/sle.c
+++ b/gcc/testsuite/gcc.target/riscv/sle.c
@@ -8,5 +8,5 @@ sle (int x, int y)
   return x <= y;
 }
 
-/* { dg-final { scan-assembler "\\sxori\\sa0,a0,1\n\\sret\n" } } */
+/* { dg-final { scan-assembler "sgt\\sa0,a0,a1" } } */
 /* { dg-final { scan-assembler-not "andi|sext\\.w" } } */

diff --git a/gcc/testsuite/gcc.target/riscv/sleu.c b/gcc/testsuite/gcc.target/riscv/sleu.c
index 301b8c32eb743447368d8cc0446dc09fb7e07561..ae00ccc20678c2a90a5f8904ebfa705c4c1a058b 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/sleu.c
+++ b/gcc/testsuite/gcc.target/riscv/sleu.c
@@ -8,5 +8,5 @@ sleu (unsigned int x, unsigned int y)
   return x <= y;
 }
 
-/* { dg-final { scan-assembler "\\sxori\\sa0,a0,1\n\\sret\n" } } */
+/* { dg-final { scan-assembler "sgtu\\sa0,a0,a1"} } */
 /* { dg-final { scan-assembler-not "andi|sext\\.w" } } */