i386: Deprecate -m[no-]avx10.1 and make -mno-avx10.1-512 to disable the whole AVX10.1

Based on the feedback we got, we would like to re-alias avx10.x to 512
bit in the future. This leaves the current avx10.1 alias to 256 bit
inconsistent. Since it has been there for GCC 14.1 and GCC 14.2,
we decide to deprecate avx10.1 alias. The current proposal is not
adding it back in the future, but it might change if necessary.

For -mno- options, it is confusing what it is disabling when it comes
to avx10. Since there is barely usage enabling AVX10 with 512 bit
then disabling it, we will only provide -mno-avx10.x options in the
future, disabling the whole AVX10.x. If someone really wants to disable
512 bit after enabling it, -mavx10.x-512 -mno-avx10.x -mavx10.x-256 is
the only way to do that since we also do not want to break the usual
expression on -m- options enabling everything mentioned.

However, for avx10.1, since we deprecated avx10.1, there is no reason
we should have -mno-avx10.1. Thus, we need to keep -mno-avx10.1-[256,512].
To avoid confusion, we will make -mno-avx10.1-512 to disable the
whole AVX10.1 set to match the future -mno-avx10.x.

gcc/ChangeLog:

	* common/config/i386/i386-common.cc
	(OPTION_MASK_ISA2_AVX2_UNSET): Change AVX10.1 unset macro.
	(OPTION_MASK_ISA2_AVX10_1_256_UNSET): Removed.
	(OPTION_MASK_ISA2_AVX10_1_512_UNSET): Removed.
	(OPTION_MASK_ISA2_AVX10_1_UNSET): New.
	(ix86_handle_option): Adjust AVX10.1 unset macro.
	* common/config/i386/i386-isas.h: Remove avx10.1.
	* config/i386/i386-options.cc
	(ix86_valid_target_attribute_inner_p): Ditto.
	(ix86_option_override_internal): Adjust warning message.
	* config/i386/i386.opt: Remove mavx10.1.
	* config/i386/i386.opt.urls: Regenerated.
	* doc/extend.texi: Remove avx10.1 and adjust doc.
	* doc/sourcebuild.texi: Ditto.

gcc/testsuite/ChangeLog:

	* gcc.target/i386/avx10_1-1.c: Change to avx10.1-256.
	* gcc.target/i386/avx10_1-13.c: Ditto.
	* gcc.target/i386/avx10_1-14.c: Ditto.
	* gcc.target/i386/avx10_1-21.c: Ditto.
	* gcc.target/i386/avx10_1-22.c: Ditto.
	* gcc.target/i386/avx10_1-23.c: Ditto.
	* gcc.target/i386/avx10_1-24.c: Ditto.
	* gcc.target/i386/avx10_1-3.c: Ditto.
	* gcc.target/i386/avx10_1-5.c: Ditto.
	* gcc.target/i386/avx10_1-6.c: Ditto.
	* gcc.target/i386/avx10_1-8.c: Ditto.
	* gcc.target/i386/avx10_1-12.c: Adjust warning message.
	* gcc.target/i386/avx10_1-19.c: Ditto.
	* gcc.target/i386/avx10_1-17.c: Adjust to no-avx10.1-512.

diff --git a/gcc/common/config/i386/i386-common.cc b/gcc/common/config/i386/i386-common.cc
index e535a3d516dbbce2d8172d0a40f4e7999f24d47a..73ba6246760000099bd77ef43aca5dcccbac418e 100644 (file)
--- a/gcc/common/config/i386/i386-common.cc
+++ b/gcc/common/config/i386/i386-common.cc
@@ -239,7 +239,7 @@ along with GCC; see the file COPYING3.  If not see
   (OPTION_MASK_ISA2_AVXIFMA_UNSET | OPTION_MASK_ISA2_AVXVNNI_UNSET \
    | OPTION_MASK_ISA2_AVXVNNIINT8_UNSET | OPTION_MASK_ISA2_AVXNECONVERT_UNSET \
    | OPTION_MASK_ISA2_AVXVNNIINT16_UNSET | OPTION_MASK_ISA2_AVX512F_UNSET \
-   | OPTION_MASK_ISA2_AVX10_1_256_UNSET)
+   | OPTION_MASK_ISA2_AVX10_1_UNSET)
 #define OPTION_MASK_ISA_AVX512F_UNSET \
   (OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_AVX512CD_UNSET \
    | OPTION_MASK_ISA_AVX512PF_UNSET | OPTION_MASK_ISA_AVX512ER_UNSET \
@@ -319,9 +319,8 @@ along with GCC; see the file COPYING3.  If not see
 #define OPTION_MASK_ISA2_APX_F_UNSET OPTION_MASK_ISA2_APX_F
 #define OPTION_MASK_ISA2_EVEX512_UNSET OPTION_MASK_ISA2_EVEX512
 #define OPTION_MASK_ISA2_USER_MSR_UNSET OPTION_MASK_ISA2_USER_MSR
-#define OPTION_MASK_ISA2_AVX10_1_256_UNSET \
-  (OPTION_MASK_ISA2_AVX10_1_256 | OPTION_MASK_ISA2_AVX10_1_512_UNSET)
-#define OPTION_MASK_ISA2_AVX10_1_512_UNSET OPTION_MASK_ISA2_AVX10_1_512
+#define OPTION_MASK_ISA2_AVX10_1_UNSET \
+  (OPTION_MASK_ISA2_AVX10_1_256 | OPTION_MASK_ISA2_AVX10_1_512)
 
 /* SSE4 includes both SSE4.1 and SSE4.2.  -mno-sse4 should the same
    as -mno-sse4.1. */
@@ -1419,8 +1418,8 @@ ix86_handle_option (struct gcc_options *opts,
        }
       else
        {
-         opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AVX10_1_256_UNSET;
-         opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVX10_1_256_UNSET;
+         opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AVX10_1_UNSET;
+         opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVX10_1_UNSET;
          opts->x_ix86_no_avx10_1_explicit = 1;
        }
       return true;
@@ -1435,8 +1434,8 @@ ix86_handle_option (struct gcc_options *opts,
        }
       else
        {
-         opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AVX10_1_512_UNSET;
-         opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVX10_1_512_UNSET;
+         opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AVX10_1_UNSET;
+         opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVX10_1_UNSET;
          opts->x_ix86_no_avx10_1_explicit = 1;
        }
       return true;

diff --git a/gcc/common/config/i386/i386-isas.h b/gcc/common/config/i386/i386-isas.h
index 9c2179a3dd86fdce2565c648e169ecb04fcbba3e..017c795e211dcc08569cfa37647e3a5a989c6c23 100644 (file)
--- a/gcc/common/config/i386/i386-isas.h
+++ b/gcc/common/config/i386/i386-isas.h
@@ -193,7 +193,6 @@ ISA_NAMES_TABLE_START
   ISA_NAMES_TABLE_ENTRY("sm4", FEATURE_SM4, P_NONE, "-msm4")
   ISA_NAMES_TABLE_ENTRY("apxf", FEATURE_APX_F, P_NONE, "-mapxf")
   ISA_NAMES_TABLE_ENTRY("usermsr", FEATURE_USER_MSR, P_NONE, "-musermsr")
-  ISA_NAMES_TABLE_ENTRY("avx10.1", FEATURE_AVX10_1_256, P_NONE, "-mavx10.1")
   ISA_NAMES_TABLE_ENTRY("avx10.1-256", FEATURE_AVX10_1_256, P_AVX10_1_256, "-mavx10.1-256")
   ISA_NAMES_TABLE_ENTRY("avx10.1-512", FEATURE_AVX10_1_512, P_AVX10_1_512, "-mavx10.1-512")
 ISA_NAMES_TABLE_END

diff --git a/gcc/config/i386/i386-options.cc b/gcc/config/i386/i386-options.cc
index a6eba1ca2b87f821a239e7073b4ba037e6d55ff2..11c6ddf0f4404ae76746e32e0c1015b34aef4dd7 100644 (file)
--- a/gcc/config/i386/i386-options.cc
+++ b/gcc/config/i386/i386-options.cc
@@ -1135,7 +1135,6 @@ ix86_valid_target_attribute_inner_p (tree fndecl, tree args, char *p_strings[],
     IX86_ATTR_ISA ("apxf", OPT_mapxf),
     IX86_ATTR_ISA ("evex512", OPT_mevex512),
     IX86_ATTR_ISA ("usermsr", OPT_musermsr),
-    IX86_ATTR_ISA ("avx10.1", OPT_mavx10_1_256),
     IX86_ATTR_ISA ("avx10.1-256", OPT_mavx10_1_256),
     IX86_ATTR_ISA ("avx10.1-512", OPT_mavx10_1_512),
 
@@ -2746,7 +2745,7 @@ ix86_option_override_internal (bool main_args_p,
          && ((OPTION_MASK_ISA2_AVX10_1_256 | OPTION_MASK_ISA2_AVX10_1_512)
              & opts->x_ix86_isa_flags2_explicit))
        {
-         warning (0, "%<-mno-avx10.1, -mno-avx10.1-256, -mno-avx10.1-512%> "
+         warning (0, "%<-mno-avx10.1-256, -mno-avx10.1-512%> "
                      "cannot disable AVX512 instructions when "
                      "%<-mavx512XXX%>");
          /* Reset those unset AVX512 flags set by AVX10 options when AVX10 is

diff --git a/gcc/config/i386/i386.opt b/gcc/config/i386/i386.opt
index d5f793a9e8b080b77bcb310a3ea7bc804be980ca..f99c4e3ae5d939d3f57734fed1f2e789e5500cb7 100644 (file)
--- a/gcc/config/i386/i386.opt
+++ b/gcc/config/i386/i386.opt
@@ -1380,8 +1380,3 @@ mavx10.1-512
 Target Mask(ISA2_AVX10_1_512) Var(ix86_isa_flags2) Save
 Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2,
 and AVX10.1-512 built-in functions and code generation.
-
-mavx10.1
-Target Alias(mavx10.1-256)
-Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2,
-and AVX10.1 built-in functions and code generation.

diff --git a/gcc/config/i386/i386.opt.urls b/gcc/config/i386/i386.opt.urls
index 81c5bb9a9270a8f13f45d0d44210a998e0c993df..3ed76635002084703777a5181629eb252b20eacd 100644 (file)
--- a/gcc/config/i386/i386.opt.urls
+++ b/gcc/config/i386/i386.opt.urls
@@ -615,6 +615,3 @@ UrlSuffix(gcc/x86-Options.html#index-mavx10_002e1-256)
 mavx10.1-512
 UrlSuffix(gcc/x86-Options.html#index-mavx10_002e1-512)
 
-mavx10.1
-UrlSuffix(gcc/x86-Options.html#index-mavx10_002e1)
-

diff --git a/gcc/doc/extend.texi b/gcc/doc/extend.texi
index 14834fc4a188b6691a35d6a771d3fa875edfa421..8bd30bb2a4686e13d38385b8a2ca791eb6d2fd1a 100644 (file)
--- a/gcc/doc/extend.texi
+++ b/gcc/doc/extend.texi
@@ -7383,20 +7383,17 @@ Enable/disable the generation of the USER_MSR instructions.
 Enable/disable the generation of the APX features, including
 EGPR, PUSH2POP2, NDD and PPX.
 
-@cindex @code{target("avx10.1")} function attribute, x86
-@item avx10.1
-@itemx no-avx10.1
-Enable/disable the generation of the AVX10.1 instructions.
-
 @cindex @code{target("avx10.1-256")} function attribute, x86
 @item avx10.1-256
 @itemx no-avx10.1-256
-Enable/disable the generation of the AVX10.1 instructions.
+Enable the generation of the AVX10.1 instructions with 256 bit support.
+Disable the generation of the AVX10.1 instructions.
 
 @cindex @code{target("avx10.1-512")} function attribute, x86
 @item avx10.1-512
 @itemx no-avx10.1-512
-Enable/disable the generation of the AVX10.1 512 bit instructions.
+Enable the generation of the AVX10.1 instructions with 512 bit support.
+Disable the generation of the AVX10.1 instructions.
 
 @cindex @code{target("cld")} function attribute, x86
 @item cld

diff --git a/gcc/doc/sourcebuild.texi b/gcc/doc/sourcebuild.texi
index 8e4e59ac44c74277b63ee4d5016e15af01792e86..5b026cfe073ecfdee9eb288d12fc865ba5bf7c59 100644 (file)
--- a/gcc/doc/sourcebuild.texi
+++ b/gcc/doc/sourcebuild.texi
@@ -2543,11 +2543,8 @@ Target supports compiling @code{avx} instructions.
 @item avx_runtime
 Target supports the execution of @code{avx} instructions.
 
-@item avx10.1
-Target supports the execution of @code{avx10.1} instructions.
-
 @item avx10.1-256
-Target supports the execution of @code{avx10.1} instructions.
+Target supports the execution of @code{avx10.1-256} instructions.
 
 @item avx10.1-512
 Target supports the execution of @code{avx10.1-512} instructions.

diff --git a/gcc/testsuite/gcc.target/i386/avx10_1-1.c b/gcc/testsuite/gcc.target/i386/avx10_1-1.c
index cfd9662bb139069b36a863dd1ca02712dd8e1759..33ce99ed60abe75f806b7c2388498d7c4a139472 100644 (file)
--- a/gcc/testsuite/gcc.target/i386/avx10_1-1.c
+++ b/gcc/testsuite/gcc.target/i386/avx10_1-1.c
@@ -1,5 +1,5 @@
 /* { dg-do compile { target { ! ia32 } } } */
-/* { dg-options "-O2 -march=x86-64 -mavx10.1" } */
+/* { dg-options "-O2 -march=x86-64 -mavx10.1-256" } */
 
 #include <immintrin.h>
 

diff --git a/gcc/testsuite/gcc.target/i386/avx10_1-12.c b/gcc/testsuite/gcc.target/i386/avx10_1-12.c
index 61f0e4db61b6bbcf5408e0b6dc6581d21f91ee31..ae1c77bbcbdc2282c3b18d69c039651924685f48 100644 (file)
--- a/gcc/testsuite/gcc.target/i386/avx10_1-12.c
+++ b/gcc/testsuite/gcc.target/i386/avx10_1-12.c
@@ -1,6 +1,6 @@
 /* { dg-do compile } */
 /* { dg-options "-march=x86-64 -mno-avx10.1-512 -mavx512f" } */
-/* { dg-warning "'-mno-avx10.1, -mno-avx10.1-256, -mno-avx10.1-512' cannot disable AVX512 instructions when '-mavx512XXX'" "" { target *-*-* } 0 } */
+/* { dg-warning "'-mno-avx10.1-256, -mno-avx10.1-512' cannot disable AVX512 instructions when '-mavx512XXX'" "" { target *-*-* } 0 } */
 /* { dg-final { scan-assembler "%zmm" } } */
 
 #include "avx10_1-2.c"

diff --git a/gcc/testsuite/gcc.target/i386/avx10_1-13.c b/gcc/testsuite/gcc.target/i386/avx10_1-13.c
index 8a1111900259ac5b1f5bdd0526eb16e01c982d31..e94ac8e1862ca7a2393dd2ee39d484ab06ca400c 100644 (file)
--- a/gcc/testsuite/gcc.target/i386/avx10_1-13.c
+++ b/gcc/testsuite/gcc.target/i386/avx10_1-13.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=x86-64 -mavx10.1" } */
+/* { dg-options "-march=x86-64 -mavx10.1-256" } */
 /* { dg-final { scan-assembler "%zmm" } } */
 
 typedef double __m512d __attribute__ ((__vector_size__ (64), __may_alias__));

diff --git a/gcc/testsuite/gcc.target/i386/avx10_1-14.c b/gcc/testsuite/gcc.target/i386/avx10_1-14.c
index 03222a7a0311d4b2ff5e9ddcfac9a7866f715ab5..76573e644fe5ec5981d33d691914d354c0895880 100644 (file)
--- a/gcc/testsuite/gcc.target/i386/avx10_1-14.c
+++ b/gcc/testsuite/gcc.target/i386/avx10_1-14.c
@@ -4,7 +4,7 @@
 
 typedef double __m512d __attribute__ ((__vector_size__ (64), __may_alias__));
 
-__attribute__ ((target ("avx10.1"))) __m512d
+__attribute__ ((target ("avx10.1-256"))) __m512d
 foo ()
 { /* { dg-warning "Vector size conflicts between AVX10.1 and AVX512, using 512 as max vector size" } */
   __m512d a, b;

diff --git a/gcc/testsuite/gcc.target/i386/avx10_1-17.c b/gcc/testsuite/gcc.target/i386/avx10_1-17.c
index a19230f597bdb90c03eee409ea55419cb10d424c..09f125215dc2a0ef45c616fedd7edb513b15f05f 100644 (file)
--- a/gcc/testsuite/gcc.target/i386/avx10_1-17.c
+++ b/gcc/testsuite/gcc.target/i386/avx10_1-17.c
@@ -4,9 +4,9 @@
 
 typedef double __m512d __attribute__ ((__vector_size__ (64), __may_alias__));
 
-__attribute__ ((target ("no-avx10.1"))) __m512d
+__attribute__ ((target ("no-avx10.1-512"))) __m512d
 foo ()
-{ /* { dg-warning "'-mno-avx10.1, -mno-avx10.1-256, -mno-avx10.1-512' cannot disable AVX512 instructions when '-mavx512XXX'" } */
+{ /* { dg-warning "'-mno-avx10.1-256, -mno-avx10.1-512' cannot disable AVX512 instructions when '-mavx512XXX'" } */
   __m512d a, b;
   a = a + b;
   return a;

diff --git a/gcc/testsuite/gcc.target/i386/avx10_1-19.c b/gcc/testsuite/gcc.target/i386/avx10_1-19.c
index 7aacc15aad944612255f6f991e1f2b9f6f7f03c6..7445ecfa548a66d613f9c60bb075efc8ee0f84f5 100644 (file)
--- a/gcc/testsuite/gcc.target/i386/avx10_1-19.c
+++ b/gcc/testsuite/gcc.target/i386/avx10_1-19.c
@@ -6,7 +6,7 @@ typedef double __m512d __attribute__ ((__vector_size__ (64), __may_alias__));
 
 __attribute__ ((target ("avx512f"))) __m512d
 foo ()
-{ /* { dg-warning "'-mno-avx10.1, -mno-avx10.1-256, -mno-avx10.1-512' cannot disable AVX512 instructions when '-mavx512XXX'" } */
+{ /* { dg-warning "'-mno-avx10.1-256, -mno-avx10.1-512' cannot disable AVX512 instructions when '-mavx512XXX'" } */
   __m512d a, b;
   a = a + b;
   return a;

diff --git a/gcc/testsuite/gcc.target/i386/avx10_1-21.c b/gcc/testsuite/gcc.target/i386/avx10_1-21.c
index 27a7265df611c3623fc2e11926eec3c3ee903c72..0a1fcc9c0f863cad9f32b549b2dd17af5c19f82f 100644 (file)
--- a/gcc/testsuite/gcc.target/i386/avx10_1-21.c
+++ b/gcc/testsuite/gcc.target/i386/avx10_1-21.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=x86-64 -mavx10.1 -mevex512 -Wno-psabi" } */
+/* { dg-options "-march=x86-64 -mavx10.1-256 -mevex512 -Wno-psabi" } */
 /* { dg-warning "Using '-mevex512' without any AVX512 features enabled together with AVX10.1 only will not enable any AVX512 or AVX10.1-512 features, using 256 as max vector size" "" { target *-*-* } 0 } */
 /* { dg-final { scan-assembler-not "%zmm" } } */
 

diff --git a/gcc/testsuite/gcc.target/i386/avx10_1-22.c b/gcc/testsuite/gcc.target/i386/avx10_1-22.c
index 796262283d6883ea1bcc84ae1b12c108412aac69..cb649dc5538e2d88e19ccadf4d08f5f4d714aa35 100644 (file)
--- a/gcc/testsuite/gcc.target/i386/avx10_1-22.c
+++ b/gcc/testsuite/gcc.target/i386/avx10_1-22.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=x86-64 -mavx10.1 -Wno-psabi" } */
+/* { dg-options "-march=x86-64 -mavx10.1-256 -Wno-psabi" } */
 /* { dg-final { scan-assembler-not "%zmm" } } */
 
 typedef double __m512d __attribute__ ((__vector_size__ (64), __may_alias__));

diff --git a/gcc/testsuite/gcc.target/i386/avx10_1-23.c b/gcc/testsuite/gcc.target/i386/avx10_1-23.c
index 6e8d64d0f34c7c509cb35aabe388cea7b63e57f9..f31c63650ab35f50b512bfa4b4247c4aace7b44b 100644 (file)
--- a/gcc/testsuite/gcc.target/i386/avx10_1-23.c
+++ b/gcc/testsuite/gcc.target/i386/avx10_1-23.c
@@ -4,7 +4,7 @@
 
 typedef double __m512d __attribute__ ((__vector_size__ (64), __may_alias__));
 
-__attribute__ ((target ("avx10.1"))) __m512d
+__attribute__ ((target ("avx10.1-256"))) __m512d
 foo ()
 { /* { dg-warning "Using '-mevex512' without any AVX512 features enabled together with AVX10.1 only will not enable any AVX512 or AVX10.1-512 features, using 256 as max vector size" "" { target *-*-* } 0 } */
   __m512d a, b;

diff --git a/gcc/testsuite/gcc.target/i386/avx10_1-24.c b/gcc/testsuite/gcc.target/i386/avx10_1-24.c
index 2e93f041760d0060aca5ff9dff61d402b92e193c..1bba0fb4b66d00b24bcc190a2faf2b48858a2a81 100644 (file)
--- a/gcc/testsuite/gcc.target/i386/avx10_1-24.c
+++ b/gcc/testsuite/gcc.target/i386/avx10_1-24.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-O2 -march=x86-64 -mavx10.1" } */
+/* { dg-options "-O2 -march=x86-64 -mavx10.1-256" } */
 /* { dg-final { scan-assembler-not "%zmm" } } */
 
 typedef float __m512 __attribute__ ((__vector_size__ (64), __may_alias__));

diff --git a/gcc/testsuite/gcc.target/i386/avx10_1-3.c b/gcc/testsuite/gcc.target/i386/avx10_1-3.c
index 3be988a1a62bfba939fc4059e00f9b0e2632e3ab..a176f2749ce68e8ae6e6e82f8fe6dae1127fc80a 100644 (file)
--- a/gcc/testsuite/gcc.target/i386/avx10_1-3.c
+++ b/gcc/testsuite/gcc.target/i386/avx10_1-3.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-O2 -march=x86-64 -mavx10.1" } */
+/* { dg-options "-O2 -march=x86-64 -mavx10.1-256" } */
 
 #include <immintrin.h>
 

diff --git a/gcc/testsuite/gcc.target/i386/avx10_1-5.c b/gcc/testsuite/gcc.target/i386/avx10_1-5.c
index 20b78ea951027d436c6f2968b5daa5e6bed6569e..3079cf14ef088c8b85df2c2e3570b4368a0841c7 100644 (file)
--- a/gcc/testsuite/gcc.target/i386/avx10_1-5.c
+++ b/gcc/testsuite/gcc.target/i386/avx10_1-5.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-O0 -march=x86-64 -mavx10.1 -Wno-psabi" } */
+/* { dg-options "-O0 -march=x86-64 -mavx10.1-256 -Wno-psabi" } */
 /* { dg-final { scan-assembler-not ".%zmm" } } */
 
 #include "avx10_1-2.c"

diff --git a/gcc/testsuite/gcc.target/i386/avx10_1-6.c b/gcc/testsuite/gcc.target/i386/avx10_1-6.c
index fbc92d5c4caed158345dfb53d8d14323f017890e..60dbd05c4a749b3e8f35f076a73ba2de4a89a380 100644 (file)
--- a/gcc/testsuite/gcc.target/i386/avx10_1-6.c
+++ b/gcc/testsuite/gcc.target/i386/avx10_1-6.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-O2 -march=x86-64 -mavx10.1" } */
+/* { dg-options "-O2 -march=x86-64 -mavx10.1-256" } */
 
 #include <immintrin.h>
 

diff --git a/gcc/testsuite/gcc.target/i386/avx10_1-8.c b/gcc/testsuite/gcc.target/i386/avx10_1-8.c
index 69b6c6a3e1ae0ef62d42239d81f5b24a79b7fc0f..ec930f72218fa04ee8f68873861fe52714b75035 100644 (file)
--- a/gcc/testsuite/gcc.target/i386/avx10_1-8.c
+++ b/gcc/testsuite/gcc.target/i386/avx10_1-8.c
@@ -1,4 +1,4 @@
 /* { dg-do compile { target { ! ia32 } } } */
-/* { dg-options "-march=x86-64 -mavx10.1 -mavx512f -mno-evex512" } */
+/* { dg-options "-march=x86-64 -mavx10.1-256 -mavx512f -mno-evex512" } */
 
 #include "avx10_1-1.c"