This patch addresses PR target/108229, which is a change in code
generation during the STV pass, due to the recently approved patch
to handle vec_select (reductions) in the vector unit. The recent
change is innocent, but exposes a latent STV "gain" calculation issue
that is benign (or closely balanced) on most microarchitectures.
The issue is when STV considers converting PLUS with a MEM operand.
On TARGET_64BIT (m=1):
addq 24(%rdi), %rdx // 4 bytes
or with -m32 (m=2)
addl 24(%esi), %eax // 3 bytes
adcl 28(%esi), %edx // 3 bytes
is being converted by STV to
vmovq 24(%rdi), %xmm5 // 5 bytes
vpaddq %xmm5, %xmm4, %xmm4 // 4 bytes
The current code in general_scalar_chain::compute_convert_gain
considers that scalar unit addition is replaced with a vector
unit addition (usually about the same cost), but doesn't consider
anything special about MEM operands, assuming that a scalar load
gains/costs nothing compared to a vector load. We can allow the
backend slightly better fine tuning by including in the gain
calculation that m scalar loads are being replaced by one vector
load, and when optimizing for size including that we're increasing
code size (e.g. an extra vmovq instruction for a MEM operand).
This patch is a win on the CSiBE benchmark when compiled with -Os.
2023-01-03 Roger Sayle <roger@nextmovesoftware.com>
gcc/ChangeLog
PR target/108229
* config/i386/i386-features.cc
(general_scalar_chain::compute_convert_gain) <case PLUS>: Consider
the gain/cost of converting a MEM operand.
igain -= vector_const_cost (XEXP (src, 0));
if (CONST_INT_P (XEXP (src, 1)))
igain -= vector_const_cost (XEXP (src, 1));
+ if (MEM_P (XEXP (src, 1)))
+ {
+ if (optimize_insn_for_size_p ())
+ igain -= COSTS_N_BYTES (m == 2 ? 3 : 5);
+ else
+ igain += m * ix86_cost->int_load[2]
+ - ix86_cost->sse_load[sse_cost_idx];
+ }
break;
case NEG: