arm64: dts: imx95: add SMMU support for NETC

The i.MX95 NETC supports SMMU, so add SMMU support.

Signed-off-by: Wei Fang <wei.fang@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>

diff --git a/arch/arm64/boot/dts/freescale/imx95-15x15-evk.dts b/arch/arm64/boot/dts/freescale/imx95-15x15-evk.dts
index 6c47f4b47356a05103dcd047955f68f8e987506f..86b6f4359cc1df86e2ff7e62a88766b34f230923 100644 (file)
--- a/arch/arm64/boot/dts/freescale/imx95-15x15-evk.dts
+++ b/arch/arm64/boot/dts/freescale/imx95-15x15-evk.dts
@@ -494,6 +494,14 @@
                  <0x60 &its 0x66 0x1>, //ENETC1 VF1
                  <0x80 &its 0x64 0x1>, //ENETC2 PF
                  <0xc0 &its 0x67 0x1>;
+       iommu-map = <0x0 &smmu 0x20 0x1>,
+                   <0x10 &smmu 0x21 0x1>,
+                   <0x20 &smmu 0x22 0x1>,
+                   <0x40 &smmu 0x23 0x1>,
+                   <0x50 &smmu 0x25 0x1>,
+                   <0x60 &smmu 0x26 0x1>,
+                   <0x80 &smmu 0x24 0x1>,
+                   <0xc0 &smmu 0x27 0x1>;
 };
 
 &netc_emdio {

diff --git a/arch/arm64/boot/dts/freescale/imx95.dtsi b/arch/arm64/boot/dts/freescale/imx95.dtsi
index f142c743f786fb5dbd67f8e52c8061bd2815a492..5a7d369581f151a04b7a2752ef14d2595f984aef 100644 (file)
--- a/arch/arm64/boot/dts/freescale/imx95.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx95.dtsi
@@ -1864,6 +1864,14 @@
                                          <0x90 &its 0x65 0x1>, //ENETC2 VF0
                                          <0xa0 &its 0x66 0x1>, //ENETC2 VF1
                                          <0xc0 &its 0x67 0x1>; //NETC Timer
+                               iommu-map = <0x0 &smmu 0x20 0x1>,
+                                           <0x10 &smmu 0x21 0x1>,
+                                           <0x20 &smmu 0x22 0x1>,
+                                           <0x40 &smmu 0x23 0x1>,
+                                           <0x80 &smmu 0x24 0x1>,
+                                           <0x90 &smmu 0x25 0x1>,
+                                           <0xa0 &smmu 0x26 0x1>,
+                                           <0xc0 &smmu 0x27 0x1>;
                                         /* ENETC0~2 and Timer BAR0 - non-prefetchable memory */
                                ranges = <0x82000000 0x0 0x4cc00000  0x0 0x4cc00000  0x0 0xe0000
                                         /* Timer BAR2 - prefetchable memory */