arm64: Provide basic EL2 setup for FEAT_{LS64, LS64_V} usage at EL0/1

Instructions introduced by FEAT_{LS64, LS64_V} is controlled by
HCRX_EL2.{EnALS, EnASR}. Configure all of these to allow usage
at EL0/1.

This doesn't mean these instructions are always available in
EL0/1 if provided. The hypervisor still have the control at
runtime.

Acked-by: Will Deacon <will@kernel.org>
Acked-by: Arnd Bergmann <arnd@arndb.de>
Acked-by: Oliver Upton <oupton@kernel.org>
Signed-off-by: Yicong Yang <yangyicong@hisilicon.com>
Signed-off-by: Zhou Wang <wangzhou1@hisilicon.com>
Signed-off-by: Will Deacon <will@kernel.org>

diff --git a/arch/arm64/include/asm/el2_setup.h b/arch/arm64/include/asm/el2_setup.h
index cacd20df1786e2241ea95206d1abef56c2d472f3..9393220de06922b034f95f5feedc2624ec846912 100644 (file)
--- a/arch/arm64/include/asm/el2_setup.h
+++ b/arch/arm64/include/asm/el2_setup.h
@@ -83,9 +83,19 @@
         /* Enable GCS if supported */
        mrs_s   x1, SYS_ID_AA64PFR1_EL1
        ubfx    x1, x1, #ID_AA64PFR1_EL1_GCS_SHIFT, #4
-       cbz     x1, .Lset_hcrx_\@
+       cbz     x1, .Lskip_gcs_hcrx_\@
        orr     x0, x0, #HCRX_EL2_GCSEn
 
+.Lskip_gcs_hcrx_\@:
+       /* Enable LS64, LS64_V if supported */
+       mrs_s   x1, SYS_ID_AA64ISAR1_EL1
+       ubfx    x1, x1, #ID_AA64ISAR1_EL1_LS64_SHIFT, #4
+       cbz     x1, .Lset_hcrx_\@
+       orr     x0, x0, #HCRX_EL2_EnALS
+       cmp     x1, #ID_AA64ISAR1_EL1_LS64_LS64_V
+       b.lt    .Lset_hcrx_\@
+       orr     x0, x0, #HCRX_EL2_EnASR
+
 .Lset_hcrx_\@:
        msr_s   SYS_HCRX_EL2, x0
 .Lskip_hcrx_\@: