#define AM62A7_SUPPORT_R_MPU_OPP BIT(1)
#define AM62A7_SUPPORT_V_MPU_OPP BIT(2)
+#define AM62L3_EFUSE_E_MPU_OPP 5
+#define AM62L3_EFUSE_O_MPU_OPP 15
+
+#define AM62L3_SUPPORT_E_MPU_OPP BIT(0)
+#define AM62L3_SUPPORT_O_MPU_OPP BIT(1)
+
#define AM62P5_EFUSE_O_MPU_OPP 15
#define AM62P5_EFUSE_S_MPU_OPP 19
#define AM62P5_EFUSE_T_MPU_OPP 20
return calculated_efuse;
}
+static unsigned long am62l3_efuse_xlate(struct ti_cpufreq_data *opp_data,
+ unsigned long efuse)
+{
+ unsigned long calculated_efuse = AM62L3_SUPPORT_E_MPU_OPP;
+
+ switch (efuse) {
+ case AM62L3_EFUSE_O_MPU_OPP:
+ calculated_efuse |= AM62L3_SUPPORT_O_MPU_OPP;
+ fallthrough;
+ case AM62L3_EFUSE_E_MPU_OPP:
+ calculated_efuse |= AM62L3_SUPPORT_E_MPU_OPP;
+ }
+
+ return calculated_efuse;
+}
+
static struct ti_cpufreq_soc_data am3x_soc_data = {
.efuse_xlate = amx3_efuse_xlate,
.efuse_fallback = AM33XX_800M_ARM_MPU_MAX_FREQ,
static const struct soc_device_attribute k3_cpufreq_soc[] = {
{ .family = "AM62X", },
{ .family = "AM62AX", },
- { .family = "AM62PX", },
{ .family = "AM62DX", },
+ { .family = "AM62LX", },
+ { .family = "AM62PX", },
{ /* sentinel */ }
};
.multi_regulator = false,
};
+static struct ti_cpufreq_soc_data am62l3_soc_data = {
+ .efuse_xlate = am62l3_efuse_xlate,
+ .efuse_offset = 0x0,
+ .efuse_mask = 0x07c0,
+ .efuse_shift = 0x6,
+ .multi_regulator = false,
+};
+
static struct ti_cpufreq_soc_data am62p5_soc_data = {
.efuse_xlate = am62p5_efuse_xlate,
.efuse_offset = 0x0,
{ .compatible = "ti,am625", .data = &am625_soc_data, },
{ .compatible = "ti,am62a7", .data = &am62a7_soc_data, },
{ .compatible = "ti,am62d2", .data = &am62a7_soc_data, },
+ { .compatible = "ti,am62l3", .data = &am62l3_soc_data, },
{ .compatible = "ti,am62p5", .data = &am62p5_soc_data, },
/* legacy */
{ .compatible = "ti,omap3430", .data = &omap34xx_soc_data, },