]> git.ipfire.org Git - thirdparty/u-boot.git/commitdiff
arm64: zynqmp: Set qspi tx-buswidth to 4
authorAmit Kumar Mahapatra <amit.kumar-mahapatra@xilinx.com>
Thu, 11 Nov 2021 13:42:48 +0000 (19:12 +0530)
committerMichal Simek <michal.simek@xilinx.com>
Mon, 15 Nov 2021 12:03:51 +0000 (13:03 +0100)
In all the ZynqMP & Versal boards dts files tx-buswidth is by default
set to 1. Due to this the framework only issues 1-1-1 write commands to
the GQSPI driver. But the GQSPI controller is capable of handling 1-4-4
write commands, so updated the tx-buswidth to 4 in ZynqMP & Versal boards
dts files. This would enable the spi-nor framework to issue 1-4-4 write
commands instead of 1-1-1. This will increase the tx data transfer rate,
as now the tx data will be transferred on four lines instead on single line.

Signed-off-by: Amit Kumar Mahapatra <amit.kumar-mahapatra@xilinx.com>
23 files changed:
arch/arm/dts/versal-vc-p-a2197-00-revA-x-prc-01-revA.dts
arch/arm/dts/versal-vc-p-a2197-00-revA-x-prc-03-revA.dts
arch/arm/dts/versal-vc-p-a2197-00-revA-x-prc-05-revA.dts
arch/arm/dts/versal-vp-x-a2785-00-revA.dts
arch/arm/dts/versal-vpk120-revA.dts
arch/arm/dts/versal-vpk120-revB.dts
arch/arm/dts/versal-x-ebm-01-revA.dtsi
arch/arm/dts/zynqmp-m-a2197-01-revA.dts
arch/arm/dts/zynqmp-m-a2197-02-revA.dts
arch/arm/dts/zynqmp-m-a2197-03-revA.dts
arch/arm/dts/zynqmp-sm-k26-revA.dts
arch/arm/dts/zynqmp-vp-x-a2785-00-revA.dts
arch/arm/dts/zynqmp-vpk120-revA.dts
arch/arm/dts/zynqmp-zc1232-revA.dts
arch/arm/dts/zynqmp-zc1254-revA.dts
arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts
arch/arm/dts/zynqmp-zcu102-revA.dts
arch/arm/dts/zynqmp-zcu104-revA.dts
arch/arm/dts/zynqmp-zcu106-revA.dts
arch/arm/dts/zynqmp-zcu111-revA.dts
arch/arm/dts/zynqmp-zcu208-revA.dts
arch/arm/dts/zynqmp-zcu216-revA.dts
arch/arm/dts/zynqmp-zcu670-revA.dts

index 92de2452b276d530d22d99288f6267ed99708bf7..861a29cceaa1575caae5878e3e0f84183a3bf423 100644 (file)
@@ -53,7 +53,7 @@
                #address-cells = <1>;
                #size-cells = <1>;
                reg = <0x0>;
-               spi-tx-bus-width = <1>;
+               spi-tx-bus-width = <4>;
                spi-rx-bus-width = <4>;
                spi-max-frequency = <35000000>;
                partition@0 {
index 84b9e28fc22e23d47f3217eb8c5edd83cce55fdc..7dd3e85d99094b7cd4b5c22177d13b319ae9f9ea 100644 (file)
@@ -65,7 +65,7 @@
                #size-cells = <1>;
                compatible = "m25p80", "jedec,spi-nor"; /* 64Mb */
                reg = <0>;
-               spi-tx-bus-width = <1>;
+               spi-tx-bus-width = <4>;
                spi-rx-bus-width = <4>;
                spi-max-frequency = <108000000>;
                partition@0 {
index 15dcc771e747d9a49b407f751639cfa88d4006d4..bcd7044f2d43843f740caadfd946f730c068d027 100644 (file)
@@ -82,7 +82,7 @@
                #size-cells = <1>;
                compatible = "m25p80", "jedec,spi-nor"; /* 16MB */
                reg = <0>;
-               spi-tx-bus-width = <1>;
+               spi-tx-bus-width = <4>;
                spi-rx-bus-width = <4>;
                spi-max-frequency = <104000000>;
                partition@0 {
index 2407bfffedb7181ed7b83f400202232c7dc21c66..c60aa9bbf681ae4118d3f3db4fffc300794b9a61 100644 (file)
@@ -50,7 +50,7 @@
                #address-cells = <1>;
                #size-cells = <1>;
                reg = <0>;
-               spi-tx-bus-width = <1>;
+               spi-tx-bus-width = <4>;
                spi-rx-bus-width = <4>;
                spi-max-frequency = <35000000>;
                partition@0 {
index 81d04158e0690955b90ad1afb74bf8bf17541558..dcaa59d375c1277fad94b4ef900138af847a0f91 100644 (file)
@@ -50,7 +50,7 @@
                #address-cells = <1>;
                #size-cells = <1>;
                reg = <0>;
-               spi-tx-bus-width = <1>;
+               spi-tx-bus-width = <4>;
                spi-rx-bus-width = <4>;
                spi-max-frequency = <35000000>;
                partition@0 {
index c0de6bc4f3dcf45ebe9fc23f529e3233be1f3aea..8f2ef3d4b3ce5a25d9e0c8300e9501a345d4a0a9 100644 (file)
@@ -50,7 +50,7 @@
                #address-cells = <1>;
                #size-cells = <1>;
                reg = <0>;
-               spi-tx-bus-width = <1>;
+               spi-tx-bus-width = <4>;
                spi-rx-bus-width = <4>;
                spi-max-frequency = <35000000>;
                partition@0 {
index 37bf825882ced5b45c89b4a2fc08ff1475ea240c..006115c1794124e543c1467ed039e69923f1ecb0 100644 (file)
@@ -19,7 +19,7 @@ flash@0 {
        #size-cells = <1>;
        compatible = "m25p80", "jedec,spi-nor"; /* 256MB */
        reg = <0>;
-       spi-tx-bus-width = <1>;
+       spi-tx-bus-width = <4>;
        spi-rx-bus-width = <4>;
        spi-max-frequency = <150000000>;
        partition@0 {
index 86f2ccf4d95121336807f848c3d088d732bab6d2..7b3722f0808b21caa94a87394e7eeb90b2fe5051 100644 (file)
@@ -77,7 +77,7 @@
                #address-cells = <1>;
                #size-cells = <1>;
                reg = <0x0>;
-               spi-tx-bus-width = <1>;
+               spi-tx-bus-width = <4>;
                spi-rx-bus-width = <4>;
                spi-max-frequency = <108000000>;
        };
index e980fb07fc308a60d614b50d056826245df2356c..11b2a58a0f060d56d18d2528c17957182a068aa4 100644 (file)
@@ -73,7 +73,7 @@
                #address-cells = <1>;
                #size-cells = <1>;
                reg = <0x0>;
-               spi-tx-bus-width = <1>;
+               spi-tx-bus-width = <4>;
                spi-rx-bus-width = <4>;
                spi-max-frequency = <108000000>;
        };
index c8c5100672fe5d2e33a1f90634f780f5d75bb896..db199c467b0d5f27407e397f711cb2da9d91cb8a 100644 (file)
@@ -73,7 +73,7 @@
                #address-cells = <1>;
                #size-cells = <1>;
                reg = <0x0>;
-               spi-tx-bus-width = <1>;
+               spi-tx-bus-width = <4>;
                spi-rx-bus-width = <4>;
                spi-max-frequency = <108000000>;
        };
index 5f55df28f3314edadb9c6c4417a49ab2b2dc1535..5bf88455bfbf17729308fe122ae3aaa5f148d730 100644 (file)
@@ -99,7 +99,7 @@
                #address-cells = <1>;
                #size-cells = <1>;
                reg = <0>;
-               spi-tx-bus-width = <1>;
+               spi-tx-bus-width = <4>;
                spi-rx-bus-width = <4>;
                spi-max-frequency = <40000000>; /* 40MHz */
                partition@0 {
index 3170e9a734006f5cebea2fd3a64cb860f055930c..d96f63eb3ed27c19a8011ad3239bfc6b4db99869 100644 (file)
@@ -88,7 +88,7 @@
                #address-cells = <1>;
                #size-cells = <1>;
                reg = <0>;
-               spi-tx-bus-width = <1>; /* maybe 4 here */
+               spi-tx-bus-width = <4>; /* maybe 4 here */
                spi-rx-bus-width = <4>;
                spi-max-frequency = <108000000>;
                partition@0 { /* for testing purpose */
index 1c0c7dac4de1fc9313e9a3f8c84431e0a7d3f663..57dede9b9864b8bf21f97198e2a9e668d6c15964 100644 (file)
                #address-cells = <1>;
                #size-cells = <1>;
                reg = <0>;
-               spi-tx-bus-width = <1>;
+               spi-tx-bus-width = <4>;
                spi-rx-bus-width = <4>;
                spi-max-frequency = <108000000>;
                partition@0 { /* for testing purpose */
index 7543855c9fda4f24df18ba30eeb8623728d4a00a..63c553f772425add261c86a8a7bbe5b1fbdb7ce7 100644 (file)
@@ -44,7 +44,7 @@
                #address-cells = <1>;
                #size-cells = <1>;
                reg = <0x0>;
-               spi-tx-bus-width = <1>;
+               spi-tx-bus-width = <4>;
                spi-rx-bus-width = <4>;
                spi-max-frequency = <108000000>; /* Based on DC1 spec */
                partition@0 { /* for testing purpose */
index 9cc1c0c6c5a7195fd57a5cb4f5a782d3205279d8..343033cc7e88d494950ff89482956ce25f915857 100644 (file)
@@ -45,7 +45,7 @@
                #address-cells = <1>;
                #size-cells = <1>;
                reg = <0x0>;
-               spi-tx-bus-width = <1>;
+               spi-tx-bus-width = <4>;
                spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */
                spi-max-frequency = <108000000>; /* Based on DC1 spec */
                partition@0 { /* for testing purpose */
index ea2dcf7c3005bbc952e13adde70bba4911ed785a..4791f482851162a95365531b20689e25479828d0 100644 (file)
                #address-cells = <1>;
                #size-cells = <1>;
                reg = <0x0>;
-               spi-tx-bus-width = <1>;
+               spi-tx-bus-width = <4>;
                spi-rx-bus-width = <4>;
                spi-max-frequency = <108000000>; /* Based on DC1 spec */
                partition@0 { /* for testing purpose */
index b73267a51e625f0929a0206aab9b5623cc3d8422..3414b4e3b3279f149a888281abdf6bd93e8d71c8 100644 (file)
                #address-cells = <1>;
                #size-cells = <1>;
                reg = <0x0>;
-               spi-tx-bus-width = <1>;
+               spi-tx-bus-width = <4>;
                spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */
                spi-max-frequency = <108000000>; /* Based on DC1 spec */
                partition@0 { /* for testing purpose */
index 0feec7e0f0b9919407fd8893d99bf76c8704bf95..2cbb13779f6c8f3ca998242cfdce957a8dd46158 100644 (file)
                #address-cells = <1>;
                #size-cells = <1>;
                reg = <0x0>;
-               spi-tx-bus-width = <1>;
+               spi-tx-bus-width = <4>;
                spi-rx-bus-width = <4>;
                spi-max-frequency = <108000000>; /* Based on DC1 spec */
                partition@0 { /* for testing purpose */
index 5994f796064596b376cc0903a1dcac2414c54014..faa5b4a40a0f86a262b9caa250708222ba33b3c2 100644 (file)
                #address-cells = <1>;
                #size-cells = <1>;
                reg = <0x0>;
-               spi-tx-bus-width = <1>;
+               spi-tx-bus-width = <4>;
                spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */
                spi-max-frequency = <108000000>; /* Based on DC1 spec */
                partition@0 { /* for testing purpose */
index eca9d8e3e9065a142341c9099722cf2a5fa7641c..722e363afde5759ff36376121a80826c9e2017fc 100644 (file)
                #address-cells = <1>;
                #size-cells = <1>;
                reg = <0x0>;
-               spi-tx-bus-width = <1>;
+               spi-tx-bus-width = <4>;
                spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */
                spi-max-frequency = <108000000>; /* Based on DC1 spec */
                partition@0 { /* for testing purpose */
index 32a6e6fb55e2fe7c8d967827406427410bf88e37..c5cdd58af6edddbbf785144e0e621e962241f2ae 100644 (file)
                #address-cells = <1>;
                #size-cells = <1>;
                reg = <0>;
-               spi-tx-bus-width = <1>;
+               spi-tx-bus-width = <4>;
                spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */
                spi-max-frequency = <108000000>; /* Based on DC1 spec */
        };
index 1e347036d0a7bb08643d3bd75da70679a2c148c5..caae16965d6f8419dd8cba51e4e583121bc56924 100644 (file)
                #address-cells = <1>;
                #size-cells = <1>;
                reg = <0x0>;
-               spi-tx-bus-width = <1>;
+               spi-tx-bus-width = <4>;
                spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */
                spi-max-frequency = <108000000>; /* Based on DC1 spec */
        };
index 6a005d5cb02aad6b861963edb3a5fead50624a04..446a492c31449d18188435eba29485ef1ff45b64 100644 (file)
                #address-cells = <1>;
                #size-cells = <1>;
                reg = <0>;
-               spi-tx-bus-width = <1>;
+               spi-tx-bus-width = <4>;
                spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */
                spi-max-frequency = <108000000>; /* Based on DC1 spec */
        };