drm/xe: Add few more GT register definitions

While we are not using these registers right now, they are part
of some runtime register lists that PF driver share with VFs on
some legacy platforms that we might want to support as SDV.

Reviewed-by: Piotr Piórkowski <piotr.piorkowski@intel.com>
Signed-off-by: Michal Wajdeczko <michal.wajdeczko@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240423180436.2089-4-michal.wajdeczko@intel.com

diff --git a/drivers/gpu/drm/xe/regs/xe_gt_regs.h b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
index 94445810ccc932826f0295ff8ffca82a03038282..6eea7a459c68fd1356e638abbade36e5e38a0723 100644 (file)
--- a/drivers/gpu/drm/xe/regs/xe_gt_regs.h
+++ b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
@@ -173,8 +173,11 @@
 #define   MAX_MSLICES                          4
 #define   MEML3_EN_MASK                                REG_GENMASK(3, 0)
 
+#define MIRROR_FUSE1                           XE_REG(0x911c)
+
 #define XELP_EU_ENABLE                         XE_REG(0x9134)  /* "_DISABLE" on Xe_LP */
 #define   XELP_EU_MASK                         REG_GENMASK(7, 0)
+#define XELP_GT_SLICE_ENABLE                   XE_REG(0x9138)
 #define XELP_GT_GEOMETRY_DSS_ENABLE            XE_REG(0x913c)
 
 #define GT_VEBOX_VDBOX_DISABLE                 XE_REG(0x9140)