riscv: zicfiss / zicfilp enumeration

This patch adds support for detecting the RISC-V ISA extensions
Zicfiss and Zicfilp.  Zicfiss and Zicfilp stand for the unprivileged
integer spec extensions for shadow stack and indirect branch tracking,
respectively.

This patch looks for Zicfiss and Zicfilp in the device tree and
accordingly lights up the corresponding bits in the cpu feature
bitmap. Furthermore this patch adds detection utility functions to
return whether shadow stack or landing pads are supported by the cpu.

Reviewed-by: Zong Li <zong.li@sifive.com>
Reviewed-by: Alexandre Ghiti <alexghiti@rivosinc.com>
Signed-off-by: Deepak Gupta <debug@rivosinc.com>
Tested-by: Andreas Korb <andreas.korb@aisec.fraunhofer.de> # QEMU, custom CVA6
Tested-by: Valentin Haudiquet <valentin.haudiquet@canonical.com>
Link: https://patch.msgid.link/20251112-v5_user_cfi_series-v23-3-b55691eacf4f@rivosinc.com
[pjw@kernel.org: updated to apply; cleaned up patch description]
Signed-off-by: Paul Walmsley <pjw@kernel.org>

diff --git a/arch/riscv/include/asm/cpufeature.h b/arch/riscv/include/asm/cpufeature.h
index 62837fa981e8ea102c1d6706631fdb1e887194ee..739fcc84bf7b28db30a3b12b5f0c33296e7c7fd8 100644 (file)
--- a/arch/riscv/include/asm/cpufeature.h
+++ b/arch/riscv/include/asm/cpufeature.h
@@ -152,4 +152,16 @@ static __always_inline bool riscv_cpu_has_extension_unlikely(int cpu, const unsi
        return __riscv_isa_extension_available(hart_isa[cpu].isa, ext);
 }
 
+static inline bool cpu_supports_shadow_stack(void)
+{
+       return (IS_ENABLED(CONFIG_RISCV_USER_CFI) &&
+               riscv_has_extension_unlikely(RISCV_ISA_EXT_ZICFISS));
+}
+
+static inline bool cpu_supports_indirect_br_lp_instr(void)
+{
+       return (IS_ENABLED(CONFIG_RISCV_USER_CFI) &&
+               riscv_has_extension_unlikely(RISCV_ISA_EXT_ZICFILP));
+}
+
 #endif

diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h
index 4369a23385413ed8020d30a288f8bb45f69304b8..7ef8e5f55c8dcf26e3dcc676db32c2f16b7e7f5a 100644 (file)
--- a/arch/riscv/include/asm/hwcap.h
+++ b/arch/riscv/include/asm/hwcap.h
@@ -110,6 +110,8 @@
 #define RISCV_ISA_EXT_ZALASR           101
 #define RISCV_ISA_EXT_ZILSD            102
 #define RISCV_ISA_EXT_ZCLSD            103
+#define RISCV_ISA_EXT_ZICFILP          104
+#define RISCV_ISA_EXT_ZICFISS          105
 
 #define RISCV_ISA_EXT_XLINUXENVCFG     127
 

diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c
index fa591aff9d335a4f451858214e48feef314eb96b..6827a577f8709c30af6f656c99dbb46b08394ff1 100644 (file)
--- a/arch/riscv/kernel/cpufeature.c
+++ b/arch/riscv/kernel/cpufeature.c
@@ -296,6 +296,24 @@ static int riscv_ext_svadu_validate(const struct riscv_isa_ext_data *data,
        return 0;
 }
 
+static int riscv_cfilp_validate(const struct riscv_isa_ext_data *data,
+                               const unsigned long *isa_bitmap)
+{
+       if (!IS_ENABLED(CONFIG_RISCV_USER_CFI))
+               return -EINVAL;
+
+       return 0;
+}
+
+static int riscv_cfiss_validate(const struct riscv_isa_ext_data *data,
+                               const unsigned long *isa_bitmap)
+{
+       if (!IS_ENABLED(CONFIG_RISCV_USER_CFI))
+               return -EINVAL;
+
+       return 0;
+}
+
 static const unsigned int riscv_a_exts[] = {
        RISCV_ISA_EXT_ZAAMO,
        RISCV_ISA_EXT_ZALRSC,
@@ -482,6 +500,10 @@ const struct riscv_isa_ext_data riscv_isa_ext[] = {
        __RISCV_ISA_EXT_DATA_VALIDATE(zicbop, RISCV_ISA_EXT_ZICBOP, riscv_ext_zicbop_validate),
        __RISCV_ISA_EXT_SUPERSET_VALIDATE(zicboz, RISCV_ISA_EXT_ZICBOZ, riscv_xlinuxenvcfg_exts, riscv_ext_zicboz_validate),
        __RISCV_ISA_EXT_DATA(ziccrse, RISCV_ISA_EXT_ZICCRSE),
+       __RISCV_ISA_EXT_SUPERSET_VALIDATE(zicfilp, RISCV_ISA_EXT_ZICFILP, riscv_xlinuxenvcfg_exts,
+                                         riscv_cfilp_validate),
+       __RISCV_ISA_EXT_SUPERSET_VALIDATE(zicfiss, RISCV_ISA_EXT_ZICFISS, riscv_xlinuxenvcfg_exts,
+                                         riscv_cfiss_validate),
        __RISCV_ISA_EXT_DATA(zicntr, RISCV_ISA_EXT_ZICNTR),
        __RISCV_ISA_EXT_DATA(zicond, RISCV_ISA_EXT_ZICOND),
        __RISCV_ISA_EXT_DATA(zicsr, RISCV_ISA_EXT_ZICSR),