RISC-V: Add Types to Un-Typed Sync Instructions:

Updates the sync instructions to ensure that no insn is left without
a type attribute. Updates a total of 9 insns to have type "atomic"
or type "multi" based on number of assembly instructions generated

Tested for regressions using rv32/64 multilib with newlib/linux.

gcc/Changelog:

	* config/riscv/sync-rvwmo.md: updated types to "multi" or
		"atomic" based on number of assembly lines generated
	* config/riscv/sync-ztso.md: likewise
	* config/riscv/sync.md: likewise

Reviewed-by: Jeff Law <jlaw@ventanamicro.com>
Signed-off-by: Edwin Lu <ewlu@rivosinc.com>

diff --git a/gcc/config/riscv/sync-rvwmo.md b/gcc/config/riscv/sync-rvwmo.md
index 1fc7cf16b5bf8505329126b0c73d6c4dc4d722d8..cb641ea9ec33e10e7a52f0c51ccd5b383fc84d5a 100644 (file)
--- a/gcc/config/riscv/sync-rvwmo.md
+++ b/gcc/config/riscv/sync-rvwmo.md
@@ -41,7 +41,8 @@
     else
        gcc_unreachable ();
   }
-  [(set (attr "length") (const_int 4))])
+  [(set_attr "type" "atomic")
+   (set (attr "length") (const_int 4))])
 
 ;; Atomic memory operations.
 
@@ -66,7 +67,7 @@
     else
       return "l<amo>\t%0,%1";
   }
-  [(set_attr "type" "atomic")
+  [(set_attr "type" "multi")
    (set (attr "length") (const_int 12))])
 
 ;; Implement atomic stores with conservative fences.
@@ -92,5 +93,5 @@
     else
       return "s<amo>\t%z1,%0";
   }
-  [(set_attr "type" "atomic")
+  [(set_attr "type" "multi")
    (set (attr "length") (const_int 12))])

diff --git a/gcc/config/riscv/sync-ztso.md b/gcc/config/riscv/sync-ztso.md
index ed94471b96be203bb74b827a0fa5899ee920ddbe..7bb15b7ab8cd2cc09ea92b47d05da9bc79d42a4d 100644 (file)
--- a/gcc/config/riscv/sync-ztso.md
+++ b/gcc/config/riscv/sync-ztso.md
@@ -35,7 +35,8 @@
     else
        gcc_unreachable ();
   }
-  [(set (attr "length") (const_int 4))])
+  [(set_attr "type" "atomic")
+   (set (attr "length") (const_int 4))])
 
 ;; Atomic memory operations.
 
@@ -56,7 +57,7 @@
     else
       return "l<amo>\t%0,%1";
   }
-  [(set_attr "type" "atomic")
+  [(set_attr "type" "multi")
    (set (attr "length") (const_int 12))])
 
 (define_insn "atomic_store_ztso<mode>"
@@ -76,5 +77,5 @@
     else
       return "s<amo>\t%z1,%0";
   }
-  [(set_attr "type" "atomic")
+  [(set_attr "type" "multi")
    (set (attr "length") (const_int 8))])

diff --git a/gcc/config/riscv/sync.md b/gcc/config/riscv/sync.md
index 2f85951508f89593307b6cf521615d31ffca76ba..6ff3493b5ceda2f39fa5d8d68a258e40f5db90a5 100644 (file)
--- a/gcc/config/riscv/sync.md
+++ b/gcc/config/riscv/sync.md
@@ -136,7 +136,8 @@
           "sc.w%J3\t%6, %7, %1\;"
           "bnez\t%6, 1b";
   }
-  [(set (attr "length") (const_int 28))])
+  [(set_attr "type" "multi")
+   (set (attr "length") (const_int 28))])
 
 (define_expand "atomic_fetch_nand<mode>"
   [(match_operand:SHORT 0 "register_operand")                        ;; old value at mem
@@ -203,7 +204,8 @@
           "sc.w%J3\t%6, %7, %1\;"
           "bnez\t%6, 1b";
   }
-  [(set (attr "length") (const_int 32))])
+  [(set_attr "type" "multi")
+   (set (attr "length") (const_int 32))])
 
 (define_expand "atomic_fetch_<atomic_optab><mode>"
   [(match_operand:SHORT 0 "register_operand")                   ;; old value at mem
@@ -310,7 +312,8 @@
           "sc.w%J3\t%5, %5, %1\;"
           "bnez\t%5, 1b";
   }
-  [(set (attr "length") (const_int 20))])
+  [(set_attr "type" "multi")
+   (set (attr "length") (const_int 20))])
 
 (define_insn "atomic_cas_value_strong<mode>"
   [(set (match_operand:GPR 0 "register_operand" "=&r")
@@ -336,7 +339,7 @@
           "bnez\t%6,1b\;"
           "1:";
   }
-  [(set_attr "type" "atomic")
+  [(set_attr "type" "multi")
    (set (attr "length") (const_int 16))])
 
 (define_expand "atomic_compare_and_swap<mode>"
@@ -497,7 +500,8 @@
           "bnez\t%7, 1b\;"
           "1:";
   }
-  [(set (attr "length") (const_int 28))])
+  [(set_attr "type" "multi")
+   (set (attr "length") (const_int 28))])
 
 (define_expand "atomic_test_and_set"
   [(match_operand:QI 0 "register_operand" "")     ;; bool output