drm/amd/display: Delete max_clks_by_state from DCE clock manager (v2)

It was not used by anything anymore.

Note that the parts of DC that need this information actually
already query it from the pplib and don't use the hardcoded
information from max_clks_by_state.

v2:
- Also delete state_dependent_clocks

Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Melissa Wen <mwen@igalia.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c
index 978bbc3079917828f0852b8e1503930d7c8e9cb1..d891b3bfe2a1fe7ec3cd24744f92d86a87c33329 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c
@@ -62,32 +62,6 @@ static const struct clk_mgr_mask disp_clk_mask = {
                CLK_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(_MASK)
 };
 
-/* Max clock values for each state indexed by "enum clocks_state": */
-static const struct state_dependent_clocks dce60_max_clks_by_state[] = {
-/* ClocksStateInvalid - should not be used */
-{ .display_clk_khz = 0, .pixel_clk_khz = 0 },
-/* ClocksStateUltraLow - not expected to be used for DCE 6.0 */
-{ .display_clk_khz = 0, .pixel_clk_khz = 0 },
-/* ClocksStateLow */
-{ .display_clk_khz = 352000, .pixel_clk_khz = 330000},
-/* ClocksStateNominal */
-{ .display_clk_khz = 600000, .pixel_clk_khz = 400000 },
-/* ClocksStatePerformance */
-{ .display_clk_khz = 600000, .pixel_clk_khz = 400000 } };
-
-/* Max clock values for each state indexed by "enum clocks_state": */
-static const struct state_dependent_clocks dce80_max_clks_by_state[] = {
-/* ClocksStateInvalid - should not be used */
-{ .display_clk_khz = 0, .pixel_clk_khz = 0 },
-/* ClocksStateUltraLow - not expected to be used for DCE 8.0 */
-{ .display_clk_khz = 0, .pixel_clk_khz = 0 },
-/* ClocksStateLow */
-{ .display_clk_khz = 352000, .pixel_clk_khz = 330000},
-/* ClocksStateNominal */
-{ .display_clk_khz = 625000, .pixel_clk_khz = 400000 },
-/* ClocksStatePerformance */
-{ .display_clk_khz = 625000, .pixel_clk_khz = 400000 } };
-
 unsigned int dentist_get_divider_from_did(unsigned int did)
 {
        if (did < DENTIST_BASE_DID_1)
@@ -268,7 +242,6 @@ static void dce_clock_read_integrated_info(struct clk_mgr_internal *clk_mgr_dce)
 {
        struct dc_debug_options *debug = &clk_mgr_dce->base.ctx->dc->debug;
        struct dc_bios *bp = clk_mgr_dce->base.ctx->dc_bios;
-       int i;
 
        if (bp->integrated_info)
                clk_mgr_dce->base.dentist_vco_freq_khz = bp->integrated_info->dentist_vco_freq;
@@ -278,40 +251,6 @@ static void dce_clock_read_integrated_info(struct clk_mgr_internal *clk_mgr_dce)
                        clk_mgr_dce->base.dentist_vco_freq_khz = 3600000;
        }
 
-       /*update the maximum display clock for each power state*/
-       for (i = 0; i < NUMBER_OF_DISP_CLK_VOLTAGE; ++i) {
-               enum dm_pp_clocks_state clk_state = DM_PP_CLOCKS_STATE_INVALID;
-
-               switch (i) {
-               case 0:
-                       clk_state = DM_PP_CLOCKS_STATE_ULTRA_LOW;
-                       break;
-
-               case 1:
-                       clk_state = DM_PP_CLOCKS_STATE_LOW;
-                       break;
-
-               case 2:
-                       clk_state = DM_PP_CLOCKS_STATE_NOMINAL;
-                       break;
-
-               case 3:
-                       clk_state = DM_PP_CLOCKS_STATE_PERFORMANCE;
-                       break;
-
-               default:
-                       clk_state = DM_PP_CLOCKS_STATE_INVALID;
-                       break;
-               }
-
-               /*Do not allow bad VBIOS/SBIOS to override with invalid values,
-                * check for > 100MHz*/
-               if (bp->integrated_info)
-                       if (bp->integrated_info->disp_clk_voltage[i].max_supported_clk >= 100000)
-                               clk_mgr_dce->max_clks_by_state[clk_state].display_clk_khz =
-                                       bp->integrated_info->disp_clk_voltage[i].max_supported_clk;
-       }
-
        if (!debug->disable_dfs_bypass && bp->integrated_info)
                if (bp->integrated_info->gpu_cap_info & DFS_BYPASS_ENABLE)
                        clk_mgr_dce->dfs_bypass_enabled = true;
@@ -419,16 +358,6 @@ void dce_clk_mgr_construct(
 {
        struct clk_mgr *base = &clk_mgr->base;
 
-       if (ctx->dce_version <= DCE_VERSION_6_4)
-               memcpy(clk_mgr->max_clks_by_state,
-                       dce60_max_clks_by_state,
-                       sizeof(dce60_max_clks_by_state));
-       else
-               memcpy(clk_mgr->max_clks_by_state,
-                       dce80_max_clks_by_state,
-                       sizeof(dce80_max_clks_by_state));
-
-
        base->ctx = ctx;
        base->funcs = &dce_funcs;
 

diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c
index d3cd542063db1221ae662dc684d28d98b3930070..d52789ba261372d3fea47e311d50bf14aa8d1f6e 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c
@@ -51,18 +51,6 @@ static const struct clk_mgr_mask disp_clk_mask = {
                CLK_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(_MASK)
 };
 
-static const struct state_dependent_clocks dce110_max_clks_by_state[] = {
-/*ClocksStateInvalid - should not be used*/
-{ .display_clk_khz = 0, .pixel_clk_khz = 0 },
-/*ClocksStateUltraLow - currently by HW design team not supposed to be used*/
-{ .display_clk_khz = 352000, .pixel_clk_khz = 330000 },
-/*ClocksStateLow*/
-{ .display_clk_khz = 352000, .pixel_clk_khz = 330000 },
-/*ClocksStateNominal*/
-{ .display_clk_khz = 467000, .pixel_clk_khz = 400000 },
-/*ClocksStatePerformance*/
-{ .display_clk_khz = 643000, .pixel_clk_khz = 400000 } };
-
 static uint32_t determine_sclk_from_bounding_box(
                const struct dc *dc,
                uint32_t required_sclk)
@@ -281,10 +269,6 @@ void dce110_clk_mgr_construct(
 {
        dce_clk_mgr_construct(ctx, clk_mgr);
 
-       memcpy(clk_mgr->max_clks_by_state,
-               dce110_max_clks_by_state,
-               sizeof(dce110_max_clks_by_state));
-
        clk_mgr->regs = &disp_clk_regs;
        clk_mgr->clk_mgr_shift = &disp_clk_shift;
        clk_mgr->clk_mgr_mask = &disp_clk_mask;

diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dce112/dce112_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dce112/dce112_clk_mgr.c
index 0f3f8df4df96a3a46715925e88d46f4e492255c7..08ed6f88025fabcad68e614a4f891704837a7c48 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dce112/dce112_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dce112/dce112_clk_mgr.c
@@ -53,19 +53,6 @@ static const struct clk_mgr_mask disp_clk_mask = {
                CLK_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(_MASK)
 };
 
-static const struct state_dependent_clocks dce112_max_clks_by_state[] = {
-/*ClocksStateInvalid - should not be used*/
-{ .display_clk_khz = 0, .pixel_clk_khz = 0 },
-/*ClocksStateUltraLow - currently by HW design team not supposed to be used*/
-{ .display_clk_khz = 389189, .pixel_clk_khz = 346672 },
-/*ClocksStateLow*/
-{ .display_clk_khz = 459000, .pixel_clk_khz = 400000 },
-/*ClocksStateNominal*/
-{ .display_clk_khz = 667000, .pixel_clk_khz = 600000 },
-/*ClocksStatePerformance*/
-{ .display_clk_khz = 1132000, .pixel_clk_khz = 600000 } };
-
-
 //TODO: remove use the two broken down functions
 int dce112_set_clock(struct clk_mgr *clk_mgr_base, int requested_clk_khz)
 {
@@ -202,10 +189,6 @@ void dce112_clk_mgr_construct(
 {
        dce_clk_mgr_construct(ctx, clk_mgr);
 
-       memcpy(clk_mgr->max_clks_by_state,
-               dce112_max_clks_by_state,
-               sizeof(dce112_max_clks_by_state));
-
        clk_mgr->regs = &disp_clk_regs;
        clk_mgr->clk_mgr_shift = &disp_clk_shift;
        clk_mgr->clk_mgr_mask = &disp_clk_mask;

diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dce120/dce120_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dce120/dce120_clk_mgr.c
index c9ba7b3fd2c32eabc51683a244dc129c322706b6..f8ef3a4710fc26d641bdba1d2817a1586033402f 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dce120/dce120_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dce120/dce120_clk_mgr.c
@@ -32,18 +32,6 @@
 #include "dce100/dce_clk_mgr.h"
 #include "dce120/dce120_hwseq.h"
 
-static const struct state_dependent_clocks dce120_max_clks_by_state[] = {
-/*ClocksStateInvalid - should not be used*/
-{ .display_clk_khz = 0, .pixel_clk_khz = 0 },
-/*ClocksStateUltraLow - currently by HW design team not supposed to be used*/
-{ .display_clk_khz = 0, .pixel_clk_khz = 0 },
-/*ClocksStateLow*/
-{ .display_clk_khz = 460000, .pixel_clk_khz = 400000 },
-/*ClocksStateNominal*/
-{ .display_clk_khz = 670000, .pixel_clk_khz = 600000 },
-/*ClocksStatePerformance*/
-{ .display_clk_khz = 1133000, .pixel_clk_khz = 600000 } };
-
 /**
  * dce121_clock_patch_xgmi_ss_info() - Save XGMI spread spectrum info
  * @clk_mgr_dce: clock manager internal structure
@@ -129,10 +117,6 @@ void dce120_clk_mgr_construct(struct dc_context *ctx, struct clk_mgr_internal *c
 {
        dce_clk_mgr_construct(ctx, clk_mgr);
 
-       memcpy(clk_mgr->max_clks_by_state,
-               dce120_max_clks_by_state,
-               sizeof(dce120_max_clks_by_state));
-
        clk_mgr->base.dprefclk_khz = 600000;
        clk_mgr->base.funcs = &dce120_funcs;
 }

diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr_internal.h b/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr_internal.h
index e01bf6bd7f3f4f2931ea21685da8e7254a26ea6d..450bce3d8e02c6c4e2914d28c100cbdf68451078 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr_internal.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr_internal.h
@@ -405,12 +405,6 @@ enum clock_type {
        clock_type_dtbclk,
 };
 
-
-struct state_dependent_clocks {
-       int display_clk_khz;
-       int pixel_clk_khz;
-};
-
 struct clk_mgr_internal {
        struct clk_mgr base;
        int smu_ver;
@@ -429,8 +423,6 @@ struct clk_mgr_internal {
        const struct clk_mgr_shift *clk_mgr_shift;
        const struct clk_mgr_mask *clk_mgr_mask;
 
-       struct state_dependent_clocks max_clks_by_state[DM_PP_CLOCKS_MAX_STATES];
-
        /*TODO: figure out which of the below fields should be here vs in asic specific portion */
        /* Cache the status of DFS-bypass feature*/
        bool dfs_bypass_enabled;