re PR target/60839 (PowerPC: internal compiler error: in extract_insn, at recog.c...

2014-04-15  Bill Schmidt  <wschmidt@linux.vnet.ibm.com>

	PR target/60839
	Revert following patch

	2014-04-02  Michael Meissner  <meissner@linux.vnet.ibm.com>

	PR target/60735
	* config/rs6000/rs6000.c (rs6000_hard_regno_mode_ok): If we have
	software floating point or no floating point registers, do not
	allow any type in the FPRs.  Eliminate a test for SPE SIMD types
	in GPRs that occurs after we tested for GPRs that would never be
	true.

	* config/rs6000/rs6000.md (mov<mode>_softfloat32, FMOVE64):
	Rewrite tests to use TARGET_DOUBLE_FLOAT and TARGET_E500_DOUBLE,
	since the FMOVE64 type is DFmode/DDmode.  If TARGET_E500_DOUBLE,
	specifically allow DDmode, since that does not use the SPE SIMD
	instructions.

From-SVN: r209425

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index b7b5a9aa503dbca5b45797953a7e2a086551c344..4479bdc74cacb78c458b94a9a888b027b7217ac7 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,23 @@
+2014-04-15  Bill Schmidt  <wschmidt@linux.vnet.ibm.com>
+
+       PR target/60839
+       Revert following patch
+
+       2014-04-02  Michael Meissner  <meissner@linux.vnet.ibm.com>
+
+       PR target/60735
+       * config/rs6000/rs6000.c (rs6000_hard_regno_mode_ok): If we have
+       software floating point or no floating point registers, do not
+       allow any type in the FPRs.  Eliminate a test for SPE SIMD types
+       in GPRs that occurs after we tested for GPRs that would never be
+       true.
+
+       * config/rs6000/rs6000.md (mov<mode>_softfloat32, FMOVE64):
+       Rewrite tests to use TARGET_DOUBLE_FLOAT and TARGET_E500_DOUBLE,
+       since the FMOVE64 type is DFmode/DDmode.  If TARGET_E500_DOUBLE,
+       specifically allow DDmode, since that does not use the SPE SIMD
+       instructions.
+
 2014-03-21  Mark Wielaard  <mjw@redhat.com>
 
        * dwarf2out.c (gen_enumeration_type_die): Add DW_AT_const_value

diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c
index f82e0a2df6e3a7b8fe481083ddb80fa618bf87c8..494efc562b7a86db2c95c6eb66ee0256816947cd 100644 (file)
--- a/gcc/config/rs6000/rs6000.c
+++ b/gcc/config/rs6000/rs6000.c
@@ -1752,9 +1752,6 @@ rs6000_hard_regno_mode_ok (int regno, enum machine_mode mode)
      modes and DImode.  */
   if (FP_REGNO_P (regno))
     {
-      if (TARGET_SOFT_FLOAT || !TARGET_FPRS)
-       return 0;
-
       if (SCALAR_FLOAT_MODE_P (mode)
          && (mode != TDmode || (regno % 2) == 0)
          && FP_REGNO_P (last_regno))
@@ -1783,6 +1780,10 @@ rs6000_hard_regno_mode_ok (int regno, enum machine_mode mode)
     return (VECTOR_MEM_ALTIVEC_OR_VSX_P (mode)
            || mode == V1TImode);
 
+  /* ...but GPRs can hold SIMD data on the SPE in one register.  */
+  if (SPE_SIMD_REGNO_P (regno) && TARGET_SPE && SPE_VECTOR_MODE (mode))
+    return 1;
+
   /* We cannot put non-VSX TImode or PTImode anywhere except general register
      and it must be able to fit within the register set.  */
 

diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index 738011c93c9666b0f0266b0f4da4f2e6cec50eb4..64c9e7c10069c34d1aa3887fbdd032e40dc238aa 100644 (file)
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -9394,9 +9394,8 @@
   [(set (match_operand:FMOVE64 0 "nonimmediate_operand" "=Y,r,r,r,r,r")
        (match_operand:FMOVE64 1 "input_operand" "r,Y,r,G,H,F"))]
   "! TARGET_POWERPC64 
-   && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) 
-       || TARGET_SOFT_FLOAT
-       || (<MODE>mode == DDmode && TARGET_E500_DOUBLE))
+   && ((TARGET_FPRS && TARGET_SINGLE_FLOAT) 
+       || TARGET_SOFT_FLOAT || TARGET_E500_SINGLE)
    && (gpc_reg_operand (operands[0], <MODE>mode)
        || gpc_reg_operand (operands[1], <MODE>mode))"
   "#"